[News] Samsung Gains Early Market Entry Advantage in the Panel-Level Packaging Sector Ahead of TSMC

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TSMC is said to be entering the fan-out panel-level packaging (FO-PLP) sector, according to a previous report from Nikkei. Now, a report from Business Korea noted that Samsung is making significant strides in the PLP field, as the tech giant acquired the PLP business from Samsung Electro-Mechanics as early as in 2019.

It is interesting to note that TSMC has returned to the development of PLP now, while this technology is actually regarded by Samsung as the “secret weapon” to challenge TSMC’s InFO-WLP technology a few years ago.

In 2015, TSMC has secured all of Apple’s A10 orders by offering the InFO-WLP (Integrated Fan-Out Wafer Level Packaging) technology. According to a previous report by Korea media outlet ETNews, Samsung was prompted to take action, making the company to cooperate with Samsung Electro-Mechanics to start developing FO-PLP technology.

In 2019, Samsung acquired the PLP business from Samsung Electro-Mechanics for 785 billion won (approximately USD 581 million), a strategic move that has paved the way for its current advancements, according to Business Korea.

At the shareholders’ meeting in March this year, Kyung Kye-hyun, the former head of Samsung Electronics’ semiconductor (DS) division, highlighted the importance of PLP technology to the industry, Business Korea noted. Kyung stated that AI semiconductor dies, which are typically 600mm x 600mm or 800mm x 800mm in size, require technologies like PLP, while Samsung is actively developing this technology and collaborating with clients.

Samsung currently offers advanced packaging services such as I-Cube 2.5D packaging, X-Cube 3D IC packaging, and 2D FOPKG packaging. For applications requiring low-power memory integration, such as mobile phones or wearable devices, Samsung already provides platforms like fan-out panel-level packaging and fan-out wafer-level packaging.

On the other hand, TSMC is reportedly collaborating with equipment and material suppliers to develop the panel-level packaging technology, though the research is still in its early stages. By using a rectangular substrate for packaging, replacing the current traditional circular wafer, more chipsets can be accommodated on a single wafer.

The report by Nikkei mentioned that TSMC is currently experimenting with rectangular substrates measuring 515 mm in length and 510 mm in width, providing more than three times the usable area of a 12-inch wafer.

For now, TSMC’s CoWoS advanced chip packaging can combine two sets of NVIDIA Blackwell GPU chips and eight sets of high-bandwidth memory (HBM). As single chips need to accommodate more transistors and integrate more memory, the mainstream 12-inch wafer might not be sufficient for packaging advanced chips soon. The reason behind TSMC’s foray into PLP research, therefore, may be interpreted as a response to the booming AI demand.

Read more

• [News] TSMC Reportedly Develops Panel-Level Packaging, Another New Chip Packaging Tech
• [News] New Battleground for TSMC, Samsung & Intel in Panel-Level Packaging

(Photo credit: Samsung)