[News] ASE Unveils IDE, Intensifies Advance Packaging Pursuit with 50% Shorter Cycles

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Advanced Semiconductor Engineering, Inc. (ASE) has unveiled its Integrated Design Ecosystem™ (IDE) – a collaborative design toolkit, meticulously tailored to enhance advanced package architecture on the VIPack™ platform. This innovation streamlines the transition from single-die SoC to multi-die disaggregated IP blocks, encompassing chiplets and memory integration through 2.5D or advanced fanout structures.

With ASE’s IDE, design efficiencies are elevated by an impressive 50%, ushering in new benchmarks for quality and user experience. This integration of cutting-edge package design tools within ASE’s workflow drastically reduces cycle times and associated customer costs.

IDE boasts an array of enhanced features, including cross-platform interaction that spans layout and verification, advanced RDL, silicon interposer auto-routing with embedded design rule checking (DRC), and Package Design Kit (PDK) integration. A noteworthy example is the Fan Out Chip on Substrate – Chip Last (FOCoS-CL) package, where design cycle timelines have been halved, dropping from 90 days to just 45.

The ASE IDE achieves significant design cycle efficiencies through two pivotal advancements. First, in the realm of Cross-Platform Interaction (Layout and Verification), ASE collaborates with leading EDA tool providers to surmount software and format compatibility challenges across various platforms. This collaborative effort streamlines the often time-consuming layout and verification processes, reducing cycle times by an impressive 50%.

Secondly, the Advanced Wafer-Level RDL/Si Interposer Auto-Routing capability automates a substantial portion of the advanced design layout, utilizing robust auto-routing and embedded design rule checks. This innovation effectively cuts design cycle times in half. As design complexities extend beyond silicon and substrates, innovative methodologies enhance electrical performance for independent routing layers within wafer-level RDL stacks and Si interposers.

ASE states that IDE is a game-changer for optimizing VIPack structures in applications such as artificial intelligence (AI), machine learning (ML), high-performance computing (HPC), 5G communication networks, autonomous transportation, and consumer electronics.

Charles Lee, ASE’s Director of Engineering & Technical Promotion, affirms, “The IDE is a crucial leap forward for ASE in delivering systematic package design enablement to our customers.”

Dr. CP Hung, Vice President of R&D at ASE, remarks, “ASE’s IDE launch underscores our commitment to delivering performance, cost-efficiency, and time-to-market advantages that keep our customers competitive. While ASE has been pioneering 2.5D production for nearly a decade, IDE’s novel design methodologies set us apart.”

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