[News] Samsung Exynos 2400 Mass Production in 4LPP+ Process, Yield Beats Last Year’s Performance

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Samsung’s flagship mobile processor, the Exynos 2400, produced using the 4LPP+ process technology, currently boasts a yield rate of approximately 60%, as per sources cited by TechNews. While this figure falls short of competitors, notably TSMC’s N4P process technology with yields surpassing 70%, it represents a significant improvement from Samsung’s own 25% yield rate over a year ago.

Samsung’s Exynos 2400 flagship mobile processor is the company’s first to utilize Fan-Out Wafer-Level Packaging (FOWLP). Samsung claims that FOWLP technology enhances heat resistance by 23% and boosts multicore performance by 8%. Consequently, the Exynos 2400 mobile processor delivers commendable performance in the latest 3DMark Wild Life benchmark tests.

In fact, Samsung previously announced plans to commence mass production of the SF3 chip in the second half of 2024, followed by the introduction of its 2-nanometer process technology between 2025 and 2026.

Industry sources cited in the report also indicate that Samsung’s foundry business has begun trial production for its second-generation 3-nanometer process technology, SF3. Furthermore, the company aims to increase its yield rate to over 60% within the next six months.

It is noteworthy that Samsung’s 3nm technology is highly aggressive compared to TSMC’s approach, which will transition to GAA transistors with its 2nm process. Samsung’s first-generation 3nm process already incorporates GAA transistor technology, specifically the MBCFET (Multi-Bridge Channel Field-Effect Transistor), known as SF3E, or 3GAE technology.

As per WeChat account ic211ic cited sources in the report, Samsung’s 3nm GAA technology utilizes wider nanosheets compared to the narrow nanowire GAA technology, offering higher performance and energy efficiency. With the 3nm GAA technology, Samsung can adjust the channel width of nanosheet transistors to optimize power consumption and performance, meeting diverse customer requirements.

Additionally, the flexibility of GAA design is highly advantageous for Design-Technology Co-Optimization (DTCO), contributing to achieving better Power, Performance, and Area (PPA) advantages.

In comparison to Samsung’s 5nm process, the first-generation 3nm process reduces power consumption by 45%, enhances performance by 23%, and decreases chip area by 16%. The upcoming second-generation 3nm process is expected to further reduce power consumption by 50%, boost performance by 30%, and reduce chip area by 35%.

(Photo credit: Samsung)