[News] Samsung Tapes out Its First High-end Mobile SoC Using 3nm Process Technology with GAA Architecture

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Samsung Electronics and Synopsys jointly announced that the former has successfully taped out its first mobile system-on-chip (SoC) with its 3nm gate-all-around (GAA) process. According to Synopsys, Samsung used the Synopsys.ai EDA suite to help with the SoC’s layouts as well as design verification, to enhance its performance.

While it is important that Samsung utilized the Synopsys.ai suite for developing high-performance SoCs, it is also momentous progress as the semiconductor heavyweight finally tapes out its advanced smartphone APs with the node.

The unnamed high-performance mobile SoC from Samsung adopts a universal CPU and GPU architecture, along with various IP modules from Synopsys. The design team not only leveraged the Synopsys.ai EDA suite for fine-tuning designs, but the Synopsys DSO.ai to maximize its output. In addition, Samsung also targeted to achieve higher performance, lower power consumption, and optimized chip area (PPA) by leveraging Synopsys’ Fusion Compiler RTL-to-GDSII solution.

Although Samsung’s foundry has been using the GAA-based SF3E node for chip production over the past two years, it has never been used to produce chips in its own smartphones, nor on other SoCs. So far, the SF3E node has only been utilized for cryptocurrency mining chips, possibly due to the initially low yields of GAAFET nodes.

Though Samsung’s press release only indicates that this SoC has been produced with GAA nodes, and the company possesses more complex SF3 processes in addition to the first generation 3-nanometer SF3E, it is reasonable to speculate that it is SF3 given the timeline.

Kijoon Hong, vice president of SLSI at Samsung Electronics, stated that the company’s long-term collaboration with Synopsys enables leading SoC designs, showcasing the highest performance, power efficiency, and chip area on advanced mobile CPU cores and SoC designs. The tape out represents an important milestone, as it demonstrates how AI-driven solutions can help realize goals. With the help of the most advanced GAA transistor architecture, ultra-high-yield design systems can be established.

This SoC chip achieves a maximum clock speed increase of 300MHz and a 10% reduction in power consumption. Samsung’s SoC development team also utilized techniques such as design partitioning optimization, multi-source clock synthesis (MSCTS), and intelligent routing optimization to reduce signal interference, while other simpler layering methods have also been employed. According to official statements, with the boost of the Synopsys Fusion Compiler, the development process could skip weeks of ‘manual’ design time.”

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(Photo credit: Samsung)