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[News] TSMC Reportedly Prepares Next-generation HBM4 Manufacturing, Utilizing 12nm and 5nm Process Nodes
TSMC reportedly plans to utilize 12nm and 5nm process nodes in manufacturing the latest HBM4 memory, according to a report by AnandTech. Citing TSMC’s executives, the world’s largest dedicated semiconductor foundry would employ two fabrication processes, N12FFC+ and N5, to integrate HBM4e memory with next-generation AI and HPC processors.
During TSMC’s presentation at its European Technology Symposium 2024, which took place on May 14th, the company revealed new details about the base dies it will produce for HBM4 using advanced logic processes.
According to a senior director of design and technology platform citing by the report, TSMC is currently working with HBM memory partners, including Micron, Samsung and SK Hynix, on advanced nodes targeting HBM4.
Earlier in mid-April, SK Hynix announced that it has signed a memorandum of understanding with TSMC for collaboration to produce next-generation HBM and enhance logic and HBM integration through advanced packaging technology. The company plans to proceed with the development of HBM4, slated to be mass produced from 2026, through this initiative.
N12FFC+, believed to be more cost-effective, is expected to achieve HBM performance, while the N5 base die could offer more logic with significantly lower power.
In the symposium, TSMC stated that its 12FFC+ process is well-suited for HBM4 performance, enabling memory vendors to construct 12-Hi (48 GB) and 16-Hi (64 GB) stacks, with per-stack bandwidth exceeding 2 TB/second. It is also optimizing CoWoS-L and CoWoS-R for HBM4, which utilize over eight layers to support HBM4’s routing of over 2,000 interconnects with proper signal integrity.
These packaging solutions is said to provide interposers that can accommodate up to 8 times the reticle size, providing ample space for as many as 12 HBM4 memory stacks.
In addition, base dies produced with the N5 process will incorporate increased logic density, lower power consumption, and enhanced performance. However, the most significant advantage may lie in the extremely small interconnect pitches achievable with such advanced process technology, ranging from 6 to 9 microns. This capability will enable N5 base dies to be paired with direct bonding, facilitating the 3D stacking of HBM4 directly on top of logic chips. Direct bonding has the potential to significantly enhance memory performance, a crucial enhancement for AI and HPC chips constantly demanding higher memory bandwidth, according to the report.
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(Photo credit: TSMC)
