[News] Samsung and SK hynix to Implement Hybrid Bonding with 3D DRAM

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Samsung and SK hynix, which have been rapidly advancing in the High-Bandwidth Memory (HBM) arena, now confirm their intention to incorporate hybrid bonding in the upcoming 3D DRAM technology, according to the latest report by The Elec.

While the current technology uses micro bump to connect DRAM modules, hybrid bonding, which could stack chips vertically by using through-silicon-via (TSV), can eliminate the need for micro bumps, significantly reducing chip thickness.

According to an earlier report by The Korean Economic Daily, currently, DRAM comprises up to 62 billion cells on a substrate with densely integrated transistors on a flat plane, posing challenges such as current leakage and interference.

In contrast, 3D DRAM stacks transistors into multiple layers, which is expected to widen the gaps between them, thereby reducing leakage and interference.

Therefore, to replace the current horizontal placement, a 3D DRAM chip triples capacity per unit area by vertically stacking cells. This also differs from HBM, which vertically connects multiple DRAM chips.

During the International Memory Workshop 2024 conference held in Seoul last week, SK hynix announced its intention to implement hybrid bonding in the production of 3D DRAM. On the other hand, Samsung plans to launch 3D DRAM in 2025, according to an earlier report by The Korean Economic Daily.

Meantime, Samsung is also exploring 4F Square DRAM and plans to integrate hybrid bonding into the production process. If successful, the tech giant could reduce die surface area by 30% compared to the currently commercialized 6F2 DRAM, according to sources cited by The Elec. Samsung is said to implement the 4F2 structure in DRAM using 10nm or finer nodes.

Read more

• [News] Samsung Considers Hybrid Bonding a Must for 16-stack HBM
• [News] The Quiet Beginning of the 3D DRAM Market Share Battle

(Photo credit: SK hynix)