[News] TSMC Reportedly Forms a Team on FOPLP Development, with Mini Line on the Road   

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With the surge in new applications like AI, advanced packaging remains a hot topic, particularly with FOPLP (Fan-Out Panel Level Packaging) technology gaining renewed attention. According to sources cited by a report from MoneyDJ, leading semiconductor foundry TSMC has officially formed a team, currently in the “Pathfinding” phase, and is planning to establish a mini line with a clear goal of advancing beyond traditional methods.

TSMC introduced the FOWLP (Fan-Out Wafer Level Packaging) technology named InFO (Integrated Fan-Out) in 2016, first used in the iPhone 7’s A10 processor. Subsequently, assembly and testing facilities actively promoted FOPLP solutions, looking to attract customers with lower production costs, yet faced ongoing technical challenges. Therefore, current terminal applications remain within mature processes, such as PMIC (Power Management IC) products.

However, per the sources cited by the same report, TSMC’s move to transition advanced packaging technology from wafer level to panel level is more than just talk—it’s becoming a reality. It is reported that TSMC is planning to use rectangular substrates measuring 515mm by 510mm, with a dedicated team already conducting research and planning to establish a mini line.

The source further mentioned that, TSMC’s development of FOPLP can be seen as a rectangular version of InFO, offering advantages such as lower unit costs and larger package sizes.

This advancement could further integrate other technologies on TSMC’s 3D fabric platform, paving the way for 2.5D/3D advanced packaging solutions to serve high-end product applications. This approach could be regarded similar to a rectangular CoWoS, currently targeted at the AI GPU sector with NVIDIA as a customer. If progress continues smoothly, these developments could potentially debut between 2026 and 2027.

On the AMD front, it is understood that their initial partners for FOPLP are ASE Technology and PowerTech Technologies, with potential applications in PC or gaming console chips. Reportedly, it’s suggested that previous packaging methods for PCs and gaming consoles primarily used FC-BGA, but upcoming new products may potentially upgrade to CoWoS level.

Sources cited by the report note that in the early stages of FOPLP, players like PowerTech Technologies, Innolux, and ASE Technology faced challenges and intermittent demand. To allocate resources effectively, equipment suppliers have been conservative in their investments in related fields, focusing mainly on adjusting specifications to meet customer demands. With TSMC now officially joining, equipment suppliers are shifting to a more proactive stance in preparation for upcoming developments.

In summary, the development of the FOPLP ecosystem hinges largely on TSMC’s role. TSMC is expected to maintain leadership in the high-end segment, while packaging and testing firms will cater to the mid-to-high-end markets. Semiconductor experts believe that in the realm of high-speed computing, CoWoS will remain mainstream for the next 3 to 5 years, with advanced 3D packaging like SoIC gaining prominence in high-end applications, solidifying TSMC’s position as a key player.

For packaging and testing companies, the key lies in product upgrades that offer cost-effectiveness. The success of FOPLP as the next generation of advanced packaging hinges on how chip manufacturers position their products, address yield issues related to warpage, and ensure overall performance and pricing that justify customer investment.

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(Photo credit: TSMC)