[News] SK hynix Reportedly Develops NAND over 400 Layers, Eyeing Mass Production Ready by 2025

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As the battle of HBM intensifies between memory giants, the competition of NAND is also heating up. According to a report by Korean media outlet etnews, SK hynix is developing 400-layer NAND flash memory, aiming to get the technology ready for mass production by the end of 2025.

Citing sources familiar with the matter, the report notes that SK hynix is currently working with supply chain partners to develop process technologies and equipment needed for 400-layer and above NANDs. As the company plans to apply hybrid bonding to achieve the breakthrough, many packaging materials and components suppliers are expected to enter the new supply chain.

According to the report, SK hynix is reviewing new materials for bonding and various technologies for connecting different wafers, including polishing, etching, deposition, and wiring. With the goal of getting the technology and infrastructure ready by the end of next year, full-scale production for the 400-layer NAND is anticipated to begin in the first half of 2026.

Currently, the Big Three in the memory sector are all trying to push the boundaries on the layers of NAND. Earlier in April, Samsung confirmed that it has begun mass production for its one-terabit (Tb) triple-level cell (TLC) 9th-generation vertical NAND (V-NAND), with the number of layers reaching 290. For now, the company aims to stack V-NAND to over 1000 layers by 2030.

Micron, on the other hand, has announced the 2650 client SSD, its first product built from 276-layer 3D NAND on July 30^th. Japanese memory chipmaker Kioxia, after successfully increasing the number of 3D NAND layers to 218 in 2023, even stated that achieving a 1,000-layer level by 2027 would be possible.

In August, 2023, SK hynix showcased its sample of the world’s first 321-layer NAND product. Now, as the limit is expected to be pushed up to 400 layers, the company plans to apply hybrid bonding to the manufacturing, which adopts a “wafer-to-wafer” (W2W) structure, etnews notes.

According to the report, until now, SK hynix has been stacking cells on top of the peripherals, the driving circuit area, using the method of “Peripheral Under Cell (PUC)” to manufacture NAND. The structure is similar to a mixed-use high-rise apartment where the peripheral (commercial space) is at the bottom and the cells (residential units) are stacked on top.

However, as the number of NAND layers increases, the peripheral is prone to be damaged during the cell stacking process due to the high heat and pressure generated during the cell process, the report explains.

Therefore, SK hynix plans to apply hybrid bonding to overcome the issues. By implementing cells and peripherals on separate wafers and then bonding the two wafers together, the method allows the peripheral wafer that drive the cells to be separately manufactured, thus enabling a stable increase in NAND layers.

Regarding the progress on the development of 400-layer NAND, SK hynix stated that it cannot confirm details about its technology development or mass production timeline, the report notes.

Read more

• [News] SK Hynix Plans to Manufacture 3D NAND over 400 Layers at -70°C with the Help of TEL
• [News] Outpacing Samsung or the End of Race? Kioxia Aims 1000-layer NAND by 2027

(Photo credit: SK hynix)