[News] TSMC Is On Track for A16 Mass Production in Late 2026 with Advanced Backside Power Delivery

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According to a report from TechNews, citing Tom’s Hardware, at its European Open Innovation Platform (OIP) Ecosystem Forum, TSMC announced that it is on track to begin mass production of the first chips using its A16 (1.6nm-class) process technology by the end of 2026.

The report notes that the new process will feature TSMC’s “Super Power Rail” (SPR) backside power delivery network (BSPDN) technology. This innovation enables enhanced power delivery and increased transistor density. However, while BSPDN addresses certain challenges, it also introduces new ones, requiring additional design work.

The A16 process will adopt a gate-all-around (GAAFET) nanosheet transistors with an architecture similar to the N2 process, and incorporate backside power rail to increase power delivery and transistor density, as mentioned by the report.

Compared to the N2P process, the report highlights that the A16 is expected to achieve an 8%-10% performance gain at the same voltage and complexity level, a 15%-20% reduction in power consumption at the same frequency and transistor count, and a 1.07x to 1.10x increase in chip density, suited for AI processors.

According to the report, TSMC’s director of design solution exploration and tech benchmarking division, Ken Wang, explained that transitioning from N2P to A16 in terms of logic layout is relatively straightforward because the cell structure and most layout patterns remain largely the same. Besides retaining the same front-side structure, the A16’s advantage lies in inheriting the NanoFlex feature from N2 device width modulation for the maximum driving strength.

TSMC’s “Super Power Rail” technology connects the backside power delivery network to each transistor’s source and drain through a specialized contact. This minimizes wire length and resistance, achieving optimal performance and power efficiency, as the report points out. From a manufacturing perspective, this implementation is one of the most complex BSPDN designs, surpassing Intel’s Power Via.

On the other hand, the advanced BSPDN implementation requires chip designers to redesign the power delivery network and route it in a new configuration. Furthermore, the report notes that the thermal mitigation must be redesigned, as the chip’s hot spots will now be situated beneath a network of wires, complicating heat dissipation.

Designing chips with BSPDN  implies the need for adopting new implementation methods, including changes to the design flow itself. According to the report, this process involves using new thermal-aware place-and-route software, new clock tree construction techniques, different IR-Drop analysis, different power domains, and new thermal analysis sign-off procedures, among other. To support this new implementation method, updated versions of EDA tools and simulation software are also essential, as the report notes.

Read more

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(Photo credit: TSMC)