[News] TSMC on Track to Qualify Ultra-Large CoWoS with 9x Reticle Sizes, 12 HBM4 Stacks by 2027

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According to a report from TechNews, citing Tom’s Hardware, at its European Open Innovation Platform (OIP) Forum, TSMC announced that its ultra-large chip-on-wafer-on-substrate (CoWoS) packaging technology would be certified by 2027, featuring 9x reticle sizes and supporting up to 12 stacks of HBM4 memory.

The report highlights that the new packaging method is designed to meet the demands of the most performance-intensive applications, enabling AI and HPC chip designers to create processors as large as the palm of a hand.

TSMC introduces new process technologies annually to meet customers’ demands for improvements in power, performance, and area (PPA). The report notes that initially, CoWoS technology in 2016 supported chip packaging with approximately 1.5x reticle size. It has since evolved to 3.3x reticle size, accommodating up to 8 stacks of HBM3.

TSMC has committed to launching a 5.5x reticle size packaging solution in 2025–2026, capable of supporting up to 12 stacks of HBM4. However, these will be overshadowed by the company’s ultimate version of CoWoS which supports system-in-packages (SiPs) of up to 9x reticle sizes, accommodating 12 or potentially even more HBM4 modules.

The report notes that the 9x reticle CoWoS technology, providing up to 7,722 mm² for chiplets, is scheduled for qualification in 2027. It is expected to be used in ultra-high-end AI processors by 2027–2028. The report highlights that with 9x reticle CoWoS, TSMC anticipates that customers will be able to stack 1.6nm-class dies on top of 2nm-class dies using TSMC’s system-on-integrated chips (SoIC) advanced packaging technologies.

(Source: TSMC)

However, according to the report, these ultra-large CoWoS packaging technologies still face significant challenges. For example, the substrate size for a 5.5x reticle CoWoS package needs to exceed 100mm x 100mm, while a 9x reticle package requires a substrate larger than 120mm x 120mm.

The report notes that as substrate sizes increase, they will impact system design and data center infrastructure, particularly in terms of power delivery and cooling systems. Advanced cooling solutions, such as liquid cooling and immersion methods, will be crucial for effectively managing these high-power processors.

Read more

• [News] TSMC Reportedly Slows Down CoWoS Capacity Expansion for 2026
• [News] TSMC’s CoWoS Prices May Rise 20%; ASE and Amkor Compete for Outsourcing Orders

(Photo credit: TSMC)