[News] NVIDIA Unveils Future AI Accelerators Design Featuring Silicon Photonics

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According to a report from TechNews, leading GPU manufacturer NVIDIA recently unveiled its vision for future artificial intelligence (AI) chip designs at the IEDM 2024 conference.

The report from TechNews, citing TechPowerUp, highlights that NVIDIA’s design proposal incorporates silicon photonics (SiPh) as I/O components. This represents a major shift from conventional interconnect technologies, which have been constrained by the physical limitations of copper.

NVIDIA’s new architecture, as noted in the report, introduces a unique way of stacking multiple GPU tiles vertically. It incorporates 12 SiPh components for chip interconnections, with each GPU tile utilizing three connections, and four GPU tiles in one tier.

As highlighted by a report from Wccftech, the SiPh components optimize the data flow between GPU tiles, which is essential for improving scalability and performance.

The design also features advanced 3D stacked DRAM, with six memory units per GPU tile, providing fine-grained memory access and significantly boosting bandwidth, as the report points out. This stacked DRAM has a direct electrical connection to the GPU tiles, similar to AMD’s 3D V-Cache technology but implemented on a larger scale.

However, the report indicates that large-scale integration of SiPh I/O components poses a particular challenge, as NVIDIA would need the capability to produce over one million SiPh connections per month to make the design commercially viable.

Furthermore, thermal management is another crucial issue, as noted in the report. The multi-tier GPU design introduces complex cooling requirements that current technologies are not yet equipped to handle. NVIDIA is actively exploring new solutions, but commercialization is expected to take time, potentially between 2028 and 2030, as the report notes.

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(Photo credit: NVIDIA)