[News] TSMC Advances in Silicon Photonics: Broadcom and NVIDIA Set to Be First Customers

According to a report by the Economic Daily News, TSMC has made significant progress in its silicon photonics strategy. The company recently achieved the integration of co-packaged optics (CPO) with advanced semiconductor packaging technologies, with sample deliveries expected to commence in early 2025. This milestone positions TSMC to usher in the 1.6T optical transmission era by the second half of 2025. Industry sources anticipate Broadcom and NVIDIA as TSMC’s first customers for these solutions.

The silicon photonics era could materialize as early as 2025. Reports indicate that TSMC, in collaboration with Broadcom, has successfully trial-produced a key CPO technology, the micro ring modulator (MRM), using its 3nm process. This development paves the way for integrating CPO with high-performance computing (HPC) or ASIC chips for AI applications, enabling a significant leap from electrical to optical signal transmission for computing tasks.

The report also highlights challenges in the production of CPO modules. The complex packaging process and low yield rates suggest that TSMC might outsource some optical engine (OE) packaging orders to other advanced packaging providers in the future.

Industry analysts cited in the report note that TSMC’s vision for silicon photonics revolves around integrating CPO modules with advanced packaging technologies such as CoWoS or SoIC. This approach eliminates the speed limitations of traditional copper interconnects. TSMC is expected to initiate sample deliveries in 2025, with 1.6T products entering mass production in the second half of the year and scaling up shipments in 2026.

The Economic Daily News further cites industry sources suggesting that NVIDIA plans to adopt CPO technology starting with its GB300 chips, set for release in the second half of 2025, and its subsequent Rubin architecture. This move aims to address the limitations of the current NVLink 72 interconnect, which connects up to 72 GB200 chips, by enhancing communication quality and mitigating signal interference and overheating issues in HPC applications.

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