[News] Samsung’s Backside Power Delivery Network Reportedly to Reduce 2nm Chip Size by 17%

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Earlier in June, Samsung updated its roadmap in the Angstrom era, stating that its 2nm node optimized with backside power delivery network (BSPDN), referred to as SF2Z, will enter mass production in 2027. Now, according to the latest report by the Korea Economic Daily, compared with the traditional front-end power delivery technology, BSPDN is said to reduce the size of Samsung’s 2nm chip by 17%.

Citing Lee Sungjae, vice president of the Foundry PDK Development Team at Samsung, on Thursday, the report also notes that by applying BSPDN to its 2nm chips, Samsung is expected to improve the product’s performance and power efficiency by 8% and 15%, respectively.

Lee’s remarks was the first time a Samsung foundry business executive provided details publicly regarding its BSPDN roadmap. The report explains that by positioning the power rails on the back of the wafer to remove bottlenecks between power and signal lines, the production of smaller chips would be easier.

However, Samsung is not the first semiconductor giant to adopt this technology. Among the Big Three in the foundry sector, Intel is at the forefront, aiming to produce chips with BSPDN technology, which it calls PowerVia, with Intel 20A (2 nm) in 2024. The tech giant also plans to implement PowerVia on Intel’s 20A along with the RibbonFET architecture for the full-surround gate transistor.

According to Intel, power lines typically occupy around 20% of the space on the chip surface, while its self-developed PowerVia’s backside power delivery technology saves this space, allowing more flexibility in the interconnect layers.

On the other hand, foundry leader TSMC reportedly plans to integrate its backside power delivery technology, Super PowerRail architecture, and nanosheet transistors in its A16 chip in 2026.

In addition to BSPDN, Samsung also revealed its roadmap about the next-generation gate-all-around (GAA) technology, which the company was first introduced in 2022, according to the report.

Samsung plans to begin mass production of 3 nm chips based on its second-generation GAA technology (SF3) in 2H24 and will also implement GAA in its upcoming 2 nm process, the report notes.

According to Lee, SF3 has enhanced chip performance by 30%, improved power efficiency by 50%, and reduced chip size by 35% compared to the chips produced with the first-generation GAA process. Coupling with the adoption of BSPDN, the two technologies can further reduce the chip size for Samsung.

Read more

• [News] Samsung Unveils Next-gen 2nm Node Roadmap; SF2Z with Backside Power Delivery to Enter Production in 2027
• [News] TSMC’s Backside Power Delivery Reportedly Set for 2026, Benefiting the Supply Chain

(Photo credit: Samsung)