[News] €9.9 Billion Investment: EU to Add a New Advanced Packaging and Testing Facility

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Recently, the European Commission approved a €1.3 billion subsidy from the Italian government to semiconductor packaging and testing company Silicon Box. The funds will support the construction of an advanced packaging and testing facility in Novara, Piedmont, Italy.

Silicon Box’s factory will utilize panel-level packaging (PLP) technology and is expected to begin construction in the second half of 2025. Initial production is planned for Q1 2028, with full capacity projected by 2033, capable of processing approximately 10,000 panels per week.

To secure direct funding from the Italian government, which accounts for about 40% of the planned €3.2 billion investment, Silicon Box has made several commitments. These include prioritizing supply to EU customers during market shortages, as required by the European Chips Act. This provision aims to enhance the EU’s semiconductor supply chain resilience and self-sufficiency.

Italy is not the only beneficiary of EU-supported semiconductor projects. Several initiatives have been approved under the European Chips Act, including:

• STMicroelectronics plans to build a SiC wafer factory in Catania, Italy, and, in partnership with GlobalFoundries, a wafer fab in Crolles, France.
• The German Ministry of Economic Affairs has approved financing for TSMC-led European Semiconductor Manufacturing Company (ESMC) to establish a wafer fab in Dresden, Germany.
• The Spanish government is offering €81 million in subsidies to Diamond Foundry Europe, a subsidiary of U.S.-based Diamond Foundry, for building a diamond wafer factory in Trujillo, Spain, with a planned investment of $850 million.

These projects demonstrate the EU’s efforts to build a “chip manufacturing alliance” while fostering regional industrial collaboration.

By increasing localized investment, promoting technological innovation, and strengthening international partnerships, Europe is striving to overcome its “chip dependency.” Projections suggest that by 2030, Europe’s share in the global semiconductor supply chain will significantly increase.

Big Panels, Big Future: Innovation in Semiconductor Packaging

The Silicon Box facility will employ panel-level packaging (PLP) technology, one of the latest innovations in semiconductor packaging.

Compared to traditional wafer-level packaging, PLP offers several advantages, including higher production efficiency, greater integration and functionality, improved thermal management and electrical performance, and notable cost benefits.

PLP technologies cater to diverse packaging needs and applications, offering unique advantages across various scenarios. Its efficiency, high integration, and performance make it widely applicable in cutting-edge fields such as 5G, AI, automotive electronics, and the Internet of Things (IoT).

Key types of panel-level packaging include:

• Panel-Level Packaging (PLP): Utilizes large substrates to enhance production efficiency, suitable for large-scale integrated circuit packaging.
• Panel-Level System-in-Package (PL-SiP): Integrates multiple chips and functional modules on a single panel, ideal for highly integrated applications like IoT and smart devices.
• Panel-Level Chip-Scale Packaging (PL-CSP): Combines PLP and chip-scale packaging benefits, providing high-density integration and space savings for AI and 5G communication chips.
• Panel-Level 3D Packaging (PL-3D): Stacks chips with vertical connections, increasing density and performance, primarily for high-performance computing and storage devices.
• Panel-Level Flip-Chip Packaging (PL-FC): Optimizes electrical performance and heat dissipation through flip-chip technology, suitable for high-speed, high-frequency chips.
• Panel-Level Optoelectronic Packaging: Supports the integration of optoelectronic components, effectively managing optical signal transmission, reducing signal loss, and improving performance for applications like optical communications, sensors, and LiDAR.

Industry experts believe that with the surging demand for semiconductor chips driven by AI, 5G, and automotive electronics, advances in packaging and testing technologies are crucial to improving efficiency and performance. Panel-level packaging, with its capability to handle larger chip sizes, is seen as a key direction for the future of semiconductor packaging and testing technologies.

(Photo credit: Silicon Box)