[News] More Complex than Intel’s? TSMC’s Super PowerRail – Elevating Chip Performance through Advanced Power Delivery

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At TSMC’s North America Technology Symposium, per a report from TechNews, the semiconductor giant unveiled its A16 process, designed to accommodate more transistors, enhance computational performance, and reduce power consumption. Of particular interest is the integration of the Super PowerRail architecture and nanosheet transistors in the A16 chip, driving faster and more efficient development of data center processors.

As Moore’s Law progresses, transistors become smaller and denser, with an increasing number of stacked layers. It may require passing through 10 to 20 layers of fstacking to provide power and data signals to the transistors below, leading to increasingly complex networks of interconnections and power lines. When electrical signals travel downward, there is IR voltage drop, resulting in power loss.

In addition to power loss, the space occupied by power supply lines is also a concern. In the later stages of chip manufacturing, complex layout of power supply lines often occupies at least 20% of resources. Solving the problem of signal network and power supply network resource conflicts, and enabling component miniaturization, has become a major challenge for chip designers. The industry, per the report, is beginning to explore the possibility of moving power supply networks to the backside of the chip.

TSMC’s A16 employs a different chip wiring. The wires that deliver power to the transistors will be located beneath the transistors instead of above them, known as backside power delivery.

One of the methods to optimize processors is to mitigate IR drop. This phenomenon lowers the voltage received by the transistors, thus lowering performance. A16’s wiring is less prone to voltage drop, and similarly, Intel also introduced backside power delivery in Intel 20A, not only simplifying power distribution but also allowing for denser chip packaging. The goal is to fit more transistors into the processor to enhance computational power.

Transistors consist of four main components: the source, drain, channel, and gate. The source is where current enters the transistor, the drain is where it exits, and the channel and gate orchestrate the movement of electrons.

TSMC’s A16 directly connects the power transmission lines to the source and drain, making it more complex than other backside power delivery methods like Intel’s. However, TSMC states that the decision for a more complex design aims to enhance chip efficiency.

Using the Super PowerRail in A16, TSMC achieves an 10% higher clock speed or a 15% to 20% decrease in power consumption at the same operating voltage (Vdd) compared to N2P. Moreover, the chip density is increased by up to 1.10 times, supporting data center products.

A16 also incorporates NanoFlex, a type of nanosheet transistor. NanoFlex provides chip designers with flexible N2 standard components, serving as the fundamental building block for chip design. Components with lower height can save space and offer higher power efficiency, while those with higher height maximize performance.

Optimizing the combination of high and low components in the same design block allows for the adjustment of power consumption, performance, and area to achieve the best balance. This capability combines various transistor types with different power efficiency, speed, and size configurations. Flexibility enables customers to tightly integrate TSMC chips with their requirements, maximizing performance.

TSMC plans to debut NanoFlex in the 2-nanometer process, with mass production scheduled for 2025. A16 is expected to launch in the second half of 2026.

Read more

• [News] Battle of the Titans in the Angstrom Era – TSMC’s A16 Competes with Intel’s 14A and Samsung’s SF1.4
• [News] The Imminent Arrival of 2-Nanometer Advanced Process