Global HBM leader, South Korea’s SK hynix, announced its financial report for the last quarter on July 25, exceeding market expectations. According to a report from Economic Daily News, the company also announced a full-scale effort to boost production of high-bandwidth memory (HBM) for AI, with this year’s capital expenditure expected to surpass initial projections. Additionally, more capacity will be allocated for HBM production.

Industry sources cited by the report also indicate that for Taiwanese manufacturers, the major global memory companies are expanding their HBM production capacity by converting existing DRAM capacity to HBM. This shift will suppress the supply of DDR4 and DDR5 DRAM, positively impacting market conditions.

Previously, as per sources cited by the Economic Daily News, it’s indicated that global memory leader Samsung plans to allocate about 30% of its existing DRAM capacity to HBM production. Now, with SK hynix reportedly making similar plans, this may benefit Taiwanese DRAM-related companies like Nanya Technology and ADATA in the future.

Reportedly, Nanya Technology is said to believe that the DRAM market has significantly improved due to the production cuts by the three major memory manufacturers—Samsung, SK hynix, and Micron—in the second half of last year, combined with the strong demand for HBM driven by generative AI. This chain reaction is spreading to various types of DRAM, and the company expects to see clear operational improvements soon.

SK hynix announced yesterday that its Q2 revenue increased by 125% year-on-year to KRW 16.4 trillion (USD 11.9 billion), setting a new record. Operating profit reached KRW 5.47 trillion, the highest since Q3 2018, significantly better than the KRW 2.9 trillion loss in the same period last year. The operating margin was 33%, exceeding expectations, mainly due to a more than 250% surge in HBM sales and an overall increase in DRAM and NAND chip prices.

SK hynix plans to begin mass production of the next-generation 12-layer HBM3e chips this quarter, enhancing its competitive edge over rivals Samsung and Micron in the design and supply of advanced memory for NVIDIA’s AI accelerators. HBM3e is expected to account for about half of all HBM chip sales this year. Additionally, capital expenditure for this year is likely to exceed initial expectations.

SK hynix predicts that the overall memory market will continue to grow in the second half of the year, with DRAM and NAND chip supply becoming tighter and demand for AI servers remaining strong.

Read more

• [News] AI Boosts HBM Demand, SK Hynix’s Q2 Profits Reach Six-Year High
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(Photo credit: SK hynix)

According to TrendForce’s latest memory spot price trend report. Details are as follows:

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Amid the wave of AI applications, the demand for high-performance memory continues to mushroom, with DRAM, represented by HBM, gaining significant traction. Meanwhile, to further meet market demand, memory manufacturers are  poised to embrace a new round of DRAM technological “revolution.”

• 4F Square DRAM being Developed Smoothly

According to a report from Korean media outlet Chosun Biz, Samsung Electronics Vice President Changsik Yoo recently announced that Samsung’s next-generation DRAM technology is progressing well. In addition to the successful mass production of 1b DRAM, the development of 4F Square DRAM technology is also proceeding smoothly, with the initial sample of 4F Square DRAM set to be developed by 2025.

Industry sources cited by WeChat account DRAMeXchange indicate that the early DRAM cell structure was 8F Square, while currently commercialized DRAM mainly uses 6F Square. Compared to these two technologies, 4F Square employs a vertical channel transistor (VCT) structure, which can reduce the chip surface area by 30%.

As the cell area decreases, DRAM density and performance increase. Therefore, driven by applications like AI, 4F Square technology is gradually sought after by major storage manufacturers.

Previously, Samsung stated that many companies are working to transition their technology to 4F Square VCT DRAM, although some challenges need to be overcome, including the development of new materials like oxide channel materials and ferroelectrics.

Industry sources believe that the initial sample of Samsung’s 4F Square DRAM in 2025 might be for internal release. Another semiconductor manufacturer, Tokyo Electron, estimates that DRAM using VCT and 4F Square technology will come out between 2027 and 2028.

Furthermore, earlier media reports mentioned that Samsung plans to apply Hybrid Bonding technology to support the production of 4F Square DRAM. Hybrid Bonding is a next-generation packaging technology referring to vertically stack chips to increase cell density and thus improve performance, which will also exert an influence on the development of HBM4 and 3D DRAM.

• HBM4 on the Horizon

In the era of AI, HBM, particularly HBM3e, has thrived in the memory market, prompting fierce competition among the three major DRAM manufacturers. A new race is now underway, primarily focusing on the next-generation HBM4 technology.

In April of this year, SK Hynix announced a partnership with TSMC to jointly develop HBM4. It is reported that the two companies will first work on performance improvements for the base die fitted at the bottom layer within the HBM package. To focus on the development of next-generation HBM4 technology, Samsung has established a new “HBM Development Team.”

In July, Choi Jang-seok, head of the New Business Planning Group in Samsung Electronics’ memory division, revealed that the company is developing a high-capacity HBM4 memory with a single stack of up to 48GB, expected to go into production next year. Recently, Samsung reportedly plans to use a 4nm advanced process to produce HBM4 logic die. Micron, on the other hand, plans to introduce HBM4 between 2025 and 2027 and transition to HBM4E by 2028.

Aside from manufacturing processes, DRAM manufacturers are actively exploring hybrid bonding technology for future HBM products. Compared to existing bonding processes, hybrid bonding eliminates the need for bumps between DRAM memory layers, instead directly connecting the upper and lower layers, copper to copper. This significantly improves signal transmission speed, better matching the high bandwidth requirements of AI computing.

In April of this year, Korean media outlet The Elec reported that Samsung successfully manufactured a 16-layer stacked HBM3 memory based on hybrid bonding technology, with the memory sample functioning normally. This 16-layer stacked hybrid bonding technology will be used to produce HBM4 at scale in the future. SK Hynix plans to adopt hybrid bonding in its HBM production by 2026. Micron is also developing HBM4 and is considering related technologies, including hybrid bonding, which are all under research at present.

• The Development of 3D DRAM Picks up Steam

3D DRAM (Three-dimensional dynamic random-access memory) represents a new DRAM technology with a novel memory cell structure. Unlike traditional DRAM, which places memory cells horizontally, 3D DRAM vertically stacks memory cells, greatly increasing storage capacity per unit area and improving efficiency. This makes it a key development for the next generation of DRAM.

In the memory market, 3D NAND Flash has already achieved commercial application, while 3D DRAM technology is still under research and development. However, as AI, big data, and other applications enjoy burgeoning growth, the demand for high-capacity, high-performance memory will surge, and 3D DRAM is expected to become a mainstream product in the memory market.

HBM technology has paved the way for the 3D evolution of DRAM, enabling DRAM to transition from traditional 2D to 3D. However, current HBM cannot be considered as true 3D DRAM technology. Samsung’s 4F Square VCT DRAM is closer to the concept of 3D DRAM, but it is not the only direction or goal for 3D DRAM. Memory manufacturers have more ideas and creativity in 3D DRAM.

Samsung plans to achieve the commercialization of 3D DRAM by 2030. In 2024, Samsung showcased two 3D DRAM technologies, including VCT and stacked DRAM. Samsung first introduced VCT technology, then upgraded to stacked DRAM by stacking multiple VCTs together to continuously improve DRAM capacity and performance.

Samsung states that stacked DRAM can fully utilize the Z-axis space, accommodating more memory cells in a smaller area, with a single chip capacity exceeding 100Gb. In May of this year, Samsung noted that it, along with other companies, successfully manufactured 16-layer 3D DRAM, but emphasized that it is not ready for mass production. 3D DRAM is expected to be produced using wafer-to-wafer hybrid bonding technology, and BSPDN (Backside Power Delivery Network) technology is also considered.

Regarding Micron, industry sources cited by DRAMeXchange reveal that Micron has filed for a 3D DRAM patent application different from Samsung’s, aiming to alter the shape of transistors and capacitors without placing cells.

BusinessKorea reported in June that SK Hynix achieved a manufacturing yield of 56.1% for its 5-layer stacked 3D DRAM. This means that out of around 1000 3D DRAMs produced on a single test wafer, about 561 viable devices were manufactured. The experimental 3D DRAM demonstrated characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix disclosed specific numbers and features of its 3D DRAM development.

Besides, American company NEO Semiconductor is also engaging in the development of 3D DRAM. Last year, NEO Semiconductor announced the launch of the world’s first 3D DRAM prototype: 3D X-DRAM. This technology resembles 3D NAND Flash, namely increasing memory capacity by stacking layers, offering high yield, low cost, and remarkably high density.

NEO Semiconductor plans to launch the first generation of 3D X-DRAM in 2025, featuring a 230-layer stack and a core capacity of 128Gb, which is several times higher than the 16Gb capacity of 2D DRAM.

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• [News] Korean Semiconductor Exports Hit a New High, with Memory Shipment up by 88.7%
• [News] Korean Advanced Packaging Industry’s Rise Delayed by TSMC and ASE Expansion

(Photo credit: SK Hynix)

According to a previous report from Bloomberg, Chinese 3D NAND Flash giant YMTC recently filed a lawsuit against American memory giant Micron in California, accusing Micron of infringing on 11 of its patents related to 3D NAND Flash and DRAM products. YMTC is requesting the court to order Micron to stop selling the infringing memory products in the United States and to pay patent royalties.

Established at the end of 2016 in Wuhan, YMTC is a major Chinese manufacturer of memory (DRAM) and flash memory (NAND Flash), supported by significant investments from the “Big Fund.” It has become a representative enterprise in China’s effort to build a local chip supply chain. However, in October 2022, the U.S. Department of Commerce added YMTC to the Entity List, preventing it from obtaining advanced equipment from U.S. companies to manufacture 3D NAND chips with 128 layers or more.

Before facing U.S. export controls, YMTC’s 128-layer 3D NAND chip products had already entered Apple’s supply chain and received technical and quality certification from Apple. At that time, Apple reportedly hoped to use YMTC’s chips not only for cost considerations but also to prevent flash memory from being overly concentrated in the hands of Samsung, SK Hynix, and Micron.

The report from Tom’s hardware states that YMTC’s current allegations assert that Micron’s 96-layer (B27A), 128-layer (B37R), 176-layer (B47R), and 232-layer (B58R) 3D NAND Flash products, as well as some DDR5 SDRAM products (Y2BM series), infringe on 11 of YMTC’s patents or patent applications filed in the United States.

Notably, last November, YMTC also filed a lawsuit against Micron and its subsidiaries in the U.S. District Court for the Northern District of California, accusing them of infringing on eight U.S. patents related to 3D NAND Flash. Additionally, per a report from South China Morning Post on June 7th of this year, YMTC filed a lawsuit in California, accusing the Denmark-based consulting firm Strand Consult, funded by Micron, of spreading false information that damaged YMTC’s market reputation and business relationships.

Industry sources cited by the Commercial Times also note that in recent years, China’s technological capabilities have significantly improved, and companies have been actively applying for patents domestically and internationally. With the support of the Chinese government, they have also started to frequently engage in patent litigation. Last year, Chinese courts received 5,062 technical intellectual property and monopoly cases.

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(Photo credit: YMTC)

TSMC continues to showcase its drive in the advanced packaging market. According to a report from MoneyDJ, TSMC has forecasted that CoWoS will remain in high demand through 2025, with potential for capacity to double in two consecutive years. TSMC is also entering the FOPLP (Fan-Out Panel-Level Packaging) space, a technology that OSATs and panel manufacturers have been developing for years, with a goal to launch it in three years.

TSMC’s stronghold on advanced packaging technologies has raised market concerns that OSATs may see their opportunities diminished as TSMC consolidates its market position.

During its earnings call, TSMC introduced “Foundry 2.0,” a new definition for the semiconductor manufacturing industry. This expanded definition now includes not only foundry services but also packaging, testing, photomask production, and other integrated component manufacturing, excluding memory production. TSMC further stated that this new definition will better reflect the company’s growing market opportunities and that the company will focus solely on cutting-edge back-end technologies.

Under this new definition, TSMC estimates the Foundry 2.0 industry will be nearly USD 250 billion in 2023, up from the previous estimate of USD 115 billion. With this new scope, the industry is expected to grow by 10% annually in 2024. Additionally, TSMC’s market share in Foundry 2.0 (logic semiconductor manufacturing) for 2023 is revised to 28%, with expectations for continued growth in 2024.

The sources cited by the report has pointed out that, observing TSMC’s process advancements, the 3nm process began mass production in 2022, with the 2nm process set for 2025, indicating a lengthening of the development cycle to three years.

Regarding the aforementioned nodes, advanced packaging may help enhance performance, reduce costs, and has the advantage of binding high-end products from top-tier clients. Additionally, the investment required for advanced packaging is significantly smaller compared to frontend technologies, making it a crucial area of focus.

The report continues to note that TSMC currently retains the majority of major CoWoS orders and collaborates with OSATs in the WoS segment. However, TSMC has reportedly yet finalized its CoW segment outsourcing orders.

Meanwhile, AMD and NVIDIA have reportedly turned to Amkor and ASE’s subsidiary, Siliconware, for CoWoS-related products, focusing on cost-sensitive high-performance products. Amkor is expected to supply about 70,000 to 80,000 units annually this year, while Siliconware can provide about 50,000 to 60,000 units.

Additionally, OSATs have been confined to mature IC FOPLP technologies for the past 7-8 years, whereas TSMC has announced it will launch its own FOPLP technology in three years.

TSMC’s planned FOPLP is a rectangular CoWoS-L concept, offering advantages in low unit cost and large-size packaging. However, it faces physical limitations such as issues in coating, spinning, and warping. TSMC, backed by a substantial equipment and materials supply chain, is well-positioned to address these challenges.

As for opportunities for other OSATs, the advanced packaging market is actually vast and can be broadly categorized into flip-chip, fan-out, fan-in, 2.5D/3D, and embedded die packaging.

These technologies can be integrated, and OSATs are not limited to TSMC’s top-tier Info, CoWoS, or SoIC technologies. OSATs can offer more cost-effective advanced packaging solutions compared to fabs, providing competitive alternatives in terms of cost and performance.

Read more

• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant
• [News] TSMC Introduces “Foundry 2.0” to Include Packaging, Testing, Mask making and Others

(Photo credit: TSMC)