Recently, it was reported that to meet the increasing demand for memory chips driven by the artificial intelligence (AI) boom, both Samsung Electronics and Micron set about ramping up their memory chip production capacity. Samsung plans to restart construction of the new Pyeongtaek plant (P5) infrastructure as early as 3Q24. Micron is building HBM testing and mass production lines at its headquarters in Boise, Idaho, U.S. and is considering producing HBM in Malaysia for the first time to meet the growing demand brought by the AI surge.

Samsung Restarts the Construction of P5 Plant

As per foreign media reports, Samsung has decided to restart the construction of the P5 infrastructure, which is expected to resume as early as 3Q24 and be completed in April 2027, though the actual date of starting production could be earlier.

Previously, P5 reportedly suspended construction at the end of January, which was said to be a temporary measure to coordinate progress, with investment not yet been finalized, as stated by Samsung at that time. Industry analysts interpret Samsung’s decision to resume P5 construction as a response to the AI-driven surge in demand for memory chip.

It is reported that the Samsung P5 plant is a large wafer fab with eight cleanrooms, while P1 to P4 only have four respectively, which makes Samsung’s plan to achieve large-scale production to meet market demand possible. However, no official announcement regarding the specific use of P5 has been disclosed so far.

According to Korean media reports, industry sources stated that Samsung held an internal management committee conference of the board of directors on May 30, during which they submitted and passed the agenda for the P5 infrastructure construction. The management committee was chaired by CEO and head of the DX division, Jong-hee Han, involving other members such as MX business head Noh Tae-moon, management support director Park Hak-gyu, and head of the memory business division Lee Jeong-bae.

Hwang Sang-joong, vice president and head of DRAM Product and Technology at Samsung, stated in March this year that HBM output for this year was expected to be 2.9 times that of last year. The company also announced its HBM roadmap, projecting that HBM shipment in 2026 would be 13.8 times the 2023 output, and by 2028, the annual HBM output would further increase to 23.1 times the 2023 level.

Micron Builds HBM Testing and Mass-Production Lines in the U.S.

On June 19, multiple media reported that Micron is building HBM testing and mass production lines at its headquarters in Boise, Idaho, and is considering producing HBM in Malaysia for the first time to meet the increased demand driven by the AI boom. Micron’s Boise wafer fab is reportedly to put into operation in 2025 and start DRAM production in 2026.

Previously, Micron announced plans to increase its HBM market share from the current “mid-single digits” to around 20% within a year. As of now, Micron has been expanding its memory capacity in various locations.

At the end of April, Micron officially announced that it had received USD 6.1 billion of government subsidies from the U.S. CHIPS and Science Act. These funds, along with additional state and local incentives, will support Micron in building a leading DRAM memory manufacturing plant in Idaho and two advanced DRAM memory manufacturing plants in Clay, New York.

The Idaho plant commenced construction in October 2023. Micron revealed that the plant is expected to run in 2025 and start DRAM production in 2026, with DRAM output increasing in line with industry demand. The New York project is in the phase of initial design, field study, and license application (NEPA application included). Construction of the wafer fab is expected to begin in 2025 and production in 2028, which will increase depending on market demand over the next decade. The press release noted that the U.S. government’s subsidies will support Micron’s plan to invest around USD 50 billion of total capital expenditures to lead domestic memory manufacturing by 2030.

In May, Japanese media Nikkan Kogyo Shimbun reported that Micron will pour JPY 600 to 800 billion to build an advanced DRAM chip plant using EUV lithography in Hiroshima, Japan. Construction is expected to start in early 2026 and be completed in late 2027 at the earliest. Japan had previously approved up to JPY 192 billion of subsidies to support Micron’s plant construction and next-generation chip production in Hiroshima.

The new Micron plant in Hiroshima will be located near the existing Fab 15, focusing on DRAM production, excluding back-end packaging and testing, with priority given to the fabrication of HBM products.

In October 2023, Micron inaugurated its second smart (Advanced assembly and test) plant in Penang, Malaysia, with an initial investment of USD 1 billion. Following the completion of the first plant, Micron allocated an additional USD 1 billion to expand the second smart plant, expanding its building area to 1.5 million square feet.

(Photo credit: Samsung)

Orders for thermal compression (TC) bonders from South Korean semiconductor equipment manufacturers are experiencing a surge, fueled by Samsung Electronics and SK Hynix ramping up their high-bandwidth memory (HBM) production. TC bonders play a pivotal role in HBM production by employing thermal compression to bond and stack chips on processed wafers, thereby significantly influencing HBM yield.

According to industry sources cited by The Chosun Daily, Samsung Electronics’ subsidiary SEMES has delivered nearly 100 TC bonders over the past year. Meanwhile, SK Hynix has inked a approximately $107.98 million contract with HANMI Semiconductor, which commands a 65% share of the TC bonder market.

Samsung Electronics and SK Hynix have developed distinct supply chains for thermal compression (TC) bonders. Samsung sources its equipment from Japan’s Toray and Sinkawa, as well as its subsidiary SEMES. In contrast, SK Hynix relies on Singapore’s ASMPT, HANMI Semiconductor, and Hanhwa Precision Machinery. Since last year, both companies have intensified localization efforts to decrease reliance on foreign equipment.

According to the Chosun Daily, HANMI Semiconductor, which co-developed TC bonders with SK Hynix in 2017, provides equipment for SK Hynix’s MR-MUF process, using an adhesive-like material for bonding DRAM chips. While HANMI’s TC bonders are compatible with both TC-NCF and MR-MUF processes, they are currently supplied only to SK Hynix and Micron.

On the other hand, SEMES, a specialist in TC bonders for the TC-NCF process used in high-bandwidth memory (HBM) stacking, supplies its equipment to Samsung. SEMES aims to exceed 250 billion won in TC bonder sales this year, up from around 100 billion won last year.

Regarding the HBM market, TrendForce notes that HBM3e may become the market mainstream for 2024, which is expected to account for 35% of advanced process wafer input by the end of 2024.

(Photo credit: SK hynix)

According to a report by Korean media outlet Business Korea, SK Hynix recently shared its latest breakthrough on its 3D DRAM at VLSI 2024 last week, announcing that the manufacturing yield of its 5-layer stacked 3D DRAM has reached 56.1%.

This means that out of roughly 1,000 3D DRAM units manufactured on a single test wafer, about 561 functional devices were successfully manufactured, the report further explains. The experimental 3D DRAM exhibits characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix has disclosed specific numbers and characteristics of its 3D DRAM development.

However, SK Hynix also noted that while 3D DRAM holds great potential, a significant amount of development is still required before it can be commercialized. The memory giant also reportedly pointed out that unlike the stable operation of 2D DRAM, 3D DRAM exhibits unstable performance characteristics, and stacking 32 to 192 layers of memory cells is necessary for widespread use.

3D DRAM is also a key development area for other major memory manufacturers like Samsung Electronics and Micron. Samsung Electronics has successfully stacked 3D DRAM up to 16 layers and plans to mass-produce 3D DRAM around 2030. Micron currently holds 30 patents related to 3D DRAM, and if there are breakthroughs in 3D DRAM technology, it could produce better DRAM products than existing ones without the need for EUV equipment.

The DRAM market remains highly concentrated, currently dominated by key players such as Samsung Electronics, SK Hynix, and Micron Technology, collectively holding over 96% of the entire market share.

Read more

• [News] Samsung and SK hynix to Implement Hybrid Bonding with 3D DRAM
• [News] The Quiet Beginning of the 3D DRAM Market Share Battle

(Photo credit: SK Hynix)

According to a report from Nikkei citing sources, memory giant Micron Technology is building a pilot production line for advanced high-bandwidth memory (HBM) in the United States and is considering producing HBM in Malaysia for the first time to capture more demand from the AI boom.

Reported on June 19, Micron is said to be expanding its HBM-related R&D facilities at its headquarters in Boise, Idaho, which include production and verification lines. Additionally, Micron is considering establishing HBM production capacity in Malaysia, where it already operates chip testing and assembly plants.

Nikkei’s report further noted that Micron’s largest HBM production facility is located in Taichung, Taiwan, where expansion efforts are also underway. Micron is said to have set a goal to triple its HBM market share to 24-26% by the end of 2025, which would bring it close to its traditional DRAM market share of approximately 23-25%.

Earlier this month, a report from a Japanese media outlet The Daily Industrial News also indicated that Micron planned to build a new DRAM plant in Hiroshima, with construction scheduled to begin in early 2026 and aiming for completion of plant buildings and first tool-in by the end of 2027.

Per industry sources cited by TechNews, Micron is expected to invest between JPY 600 to 800 billion in the new facility, located adjacent to the existing Fab15 facility. Initially, the new plant will focus on DRAM production, excluding backend packaging and testing, with a capacity emphasis on HBM products.

Micron, along with SK Hynix, has reportedly received certification from NVIDIA to produce HBM3e for the AI chip “H200.” Samsung Electronics has not yet received approval from NVIDIA; its less advanced HBM3 and HBM2e are currently primarily supplied to AMD, Google, and Amazon.

Read more

• [News] HBM Supply Shortage Prompts Micron’s Expansion, Expected Schedule in Japan and Taiwan Revealed
• [News] Micron Slightly Raises Capital Expenditure for 2024, HBM Expected to Further Drive Revenue Growth in 2025

(Photo credit: Micron)

Samsung and SK hynix, which have been rapidly advancing in the High-Bandwidth Memory (HBM) arena, now confirm their intention to incorporate hybrid bonding in the upcoming 3D DRAM technology, according to the latest report by The Elec.

While the current technology uses micro bump to connect DRAM modules, hybrid bonding, which could stack chips vertically by using through-silicon-via (TSV), can eliminate the need for micro bumps, significantly reducing chip thickness.

According to an earlier report by The Korean Economic Daily, currently, DRAM comprises up to 62 billion cells on a substrate with densely integrated transistors on a flat plane, posing challenges such as current leakage and interference.

In contrast, 3D DRAM stacks transistors into multiple layers, which is expected to widen the gaps between them, thereby reducing leakage and interference.

Therefore, to replace the current horizontal placement, a 3D DRAM chip triples capacity per unit area by vertically stacking cells. This also differs from HBM, which vertically connects multiple DRAM chips.

During the International Memory Workshop 2024 conference held in Seoul last week, SK hynix announced its intention to implement hybrid bonding in the production of 3D DRAM. On the other hand, Samsung plans to launch 3D DRAM in 2025, according to an earlier report by The Korean Economic Daily.

Meantime, Samsung is also exploring 4F Square DRAM and plans to integrate hybrid bonding into the production process. If successful, the tech giant could reduce die surface area by 30% compared to the currently commercialized 6F2 DRAM, according to sources cited by The Elec. Samsung is said to implement the 4F2 structure in DRAM using 10nm or finer nodes.

Read more

• [News] Samsung Considers Hybrid Bonding a Must for 16-stack HBM
• [News] The Quiet Beginning of the 3D DRAM Market Share Battle

(Photo credit: SK hynix)