• The continuous AI integration of smart homes accelerates with the Matter protocol.

In the context of the modern era, smart homes are the AI applications that come second only to smartphones and smartwatches. As the penetration rate of smart home devices increases, more and more AI-enabled devices are permeating into human life, ushering in a large-scale era of personalization. The realization of smart homes not only requires smart appliances but also sensors and energy management systems. The deployment of AI will enhance recognition and control.

The diverse application scenarios of smart homes result in a wide variety of products. Despite the vast market size, there is an issue of product ecosystem fragmentation, leading to slow deployment. This can be addressed through the integration of the smart home market via the Matter protocol. As Matter facilitates communication between different devices through software protocols, the importance of software in devices will increase with the product’s AI capabilities, catering to the demands of edge AI applications.

• The RISC-V architecture is on the rise, and the form of MCUs with NPUs will continue to proliferate.

Although CPUs in MCUs are currently dominated by the Arm architecture, open-source RISC-V is gradually rising. In addition to its features such as customization, modularity, and cost-effectiveness, RISC-V is expected to become one of the advantages in smart home applications. It continues to gain support and application from many major manufacturers, expanding the ecosystem of the RISC-V architecture.

Because TinyML models are much smaller than general-purpose AI, they do not require a large amount of computational resources for deployment. This makes them suitable for IoT devices or smart homes that require large-scale deployment, with significant advantages in both technology and cost. Furthermore, with the diverse range of products in smart homes and the increasing demand for product functionality, the form of MCUs equipped with NPUs will become increasingly common as they adapt to the product’s uniqueness and evolve with AI integration.

With the increasing demand for massive computing in fields such as AI, communication, and autonomous vehicles, the evolution of integrated circuits (ICs) has reached a physical limit under the premise of Moore’s Law. How can this limit be surpassed? The answer lies in the realm of optics. Currently, many domestic and international companies are actively embracing “Silicon Photonics” technology. When electronics meet photons, it not only addresses the signal transmission loss issue but is also considered a key technology that could usher in a new era, potentially revolutionizing the future world.

Integrated circuits (ICs) cram millions of transistors onto a single chip, performing various complex calculations. Silicon Photonics, on the other hand, represents integrated “light” paths, where light-conductive pathways are consolidated. In simple terms, it is a technology that converts “electronic signals” into “optical signals” on a silicon platform, facilitating the transmission of both electrical and optical signals.

As technology rapidly advances and computer processing speeds increase, communication between chips has become a critical factor in computing performance. For instance, when ChatGPT was first launched, there were issues with lag and interruptions during the question and answer process, which were related to data transmission problems. Therefore, as AI technology continues to evolve, maintaining computational speed is a crucial aspect of embracing the AI era.

Silicon Photonics has the potential to enhance the speed of optoelectronic transmission, addressing the signal loss and heat issues associated with copper wiring in current computer components. Consequently, semiconductor giants such as TSMC and Intel have already invested in related research and development efforts. In this context, we interviewed Dr. Fang Yen Hsiang, director of the Opto-Electronics Micro Device & System Application Division and Electronic and Optoelectronic System Research Laboratories at the Industrial Technology Research Institute (ITRI), to gain insights into this critical technology.

What Is the Relationship Between Silicon Photonics and Optical Transceivers?

An optical transceiver module comprises various components, including optical receivers, amplifiers, modulators, and more. In the past, these components were individually scattered on a PCB (printed circuit board). However, to reduce power consumption, increase data transmission speed, and minimize transmission loss and signal delay, these components have been integrated into a single silicon chip. Fang emphasizes that this integration is the core of Silicon Photonics.

Integrated Circuits’ Next Step: The Three Stages of Silicon Photonics

• Silicon Photonics Stage 1: Upgrading from Traditional Pluggable Modules

Silicon Photonics has been quietly developing for over 20 years. The traditional Silicon Photonics pluggable optical transceiver modules look very much like USB interfaces and connect to two optical fibers—one for incoming and one for outgoing light. However, the electrical transmission path in pluggable modules had a long distance before reaching the switch inside the server. This resulted in significant signal loss at high speeds. To minimize this loss, Silicon Photonics components have been moved closer to the server’s switch, shortening the electrical transmission path. Consequently, the original pluggable modules now only contain optical fibers.

This approach aligns with the actively developing “Co-Packaged Optics” (CPO) technology in the industry. The main idea is to assemble electronic integrated circuits (EIC) and photonic integrated circuits (PIC) onto the same substrate, creating a co-packaged board that integrates chips and modules. This co-packaging, known as CPO light engines (depicted in figure “d” below), replaces optical transceivers and brings optical engines closer to CPU/GPU chips (depicted in figure “d” as chips). This reduces transmission paths, minimizes transmission loss, and reduces signal delay.

According to ITRI, this technology reduces costs, increases data transmission by over 8 times, provides more than 30 times the computing power, and saves 50% in power consumption. However, the integration of chipsets is still a work in progress, and refining CPO technology will be the next important step in the development of Silicon Photonics.

• Solving the CPO Bottleneck and Beyond – Silicon Photonics Stage 2: Addressing CPU/GPU Transmission Issues

Currently, Silicon Photonics primarily addresses the signal delay challenges of plug-in modules. As technology progresses, the next stage will involve solving the electrical signal transmission issues between CPUs and GPUs. Academics point out that chip-to-chip communication is primarily based on electrical signals. Therefore, the next step is to enable internal chip-to-chip communication between GPUs and CPUs using optical waveguides, converting all electrical signals into optical signals to accelerate AI computations and address the current computational bottleneck.

• Silicon Photonics Ultimate Stage 3: The Arrival of the All-Optical Network (AON) Era

As technology advances even further, we will usher in the era of the “All-Optical Network” (AON). This means that all chip-to-chip communication will rely on optical signals, including random storage, transmission, switching, and processing, all of which will be transmitted as optical signals. Japan has already been actively implementing Silicon Photonics in preparation for the full transition to all-optical networks in this context.

Where Does Silicon Photonics Currently Face Technological Challenges?

Currently, Silicon Photonics faces several challenges related to component integration. First and foremost is the issue of communication. Dr. Fang Yen Hsiang provides an example: semiconductor manufacturers understand electronic processes, but because the performance of photonic components is sensitive to factors such as temperature and path length, and because linewidth and spacing have a significant impact on optical signal transmission, a communication platform is needed. This platform would provide design specifications, materials, parameters, and other information to facilitate communication between electronic and photonic manufacturers.

Furthermore, Silicon Photonics is currently being applied in niche markets, and various packaging processes and material standards are still being established. Most of the wafer foundries that provide Silicon Photonics chip fabrication belong to the realm of customized services and may not be suitable for use by other customers. The lack of a unified platform could hinder the development of Silicon Photonics technology.

In addition to the lack of a common platform, high manufacturing costs, integrated light sources, component performance, material compatibility, thermal effects, and reliability are also challenges in Silicon Photonics manufacturing processes. With ongoing technological progress and innovation, it is expected that these bottlenecks will be overcome in the coming years to a decade.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: Google)

According to the news from ChinaTimes, Qualcomm announced on the 11th that it has reached a three-year agreement with Apple to supply 5G communication chips for Apple’s smartphones from 2024 to 2026. This also implies that Apple’s efforts to develop its own 5G modem chips may fall through, and the contract manufacturer TSMC stands to benefit the most.

Qualcomm did not disclose the value of this deal but mentioned that the terms of the agreement are similar to previous ones. Previous supply agreements have been highly profitable for Qualcomm but costly for Apple. According to UBS estimates from last month, Qualcomm’s sales of modem chips to Apple in the previous fiscal year amounted to $7.26 billion, accounting for approximately 16% of the company’s revenue.

This also highlights that Apple’s progress in developing modem chips may not be as expected, leading to a delay in their use in their flagship smartphones. Currently, Apple’s iPhones use 5G modem chips from Qualcomm.

Only a few companies worldwide have the capability to produce communication chips, including Qualcomm, MediaTek, and Samsung. In 2019, Apple acquired Intel’s smartphone modem business for $1 billion, along with 2,200 employees and a series of patents. Intel faced difficulties in developing 5G modem chips, resulting in annual losses of around $1 billion.

The market expects Apple to gradually reduce its reliance on third-party chip suppliers. Qualcomm originally estimated that by 2023, their 5G chips would make up only 20% of iPhones. However, Qualcomm’s CFO stated in November of the previous year that “most” of Apple’s phones in 2023 would contain their chips.

(Source: https://www.chinatimes.com/newspapers/20230912000097-260202?chdtv)

On August 29, 2023, Huawei quietly launched its new smartphone, the Huawei Mate 60 Pro, on its official website without the usual fanfare associated with new product releases. Unlike previous events or those held by other brands, Huawei chose to communicate with consumers solely through a letter. What intrigued the market most was the specification of the new device’s System-on-Chip (SoC). Initially, Huawei did not provide any official information about it. However, the release of this new smartphone demonstrates China’s determination to achieve semiconductor self-sufficiency.

Key Insights from TrendForce:

• Overcoming U.S. Sanctions, Huawei Makes a Comeback

In the past, Huawei secured its position as the second-largest player in the global smartphone market by leveraging the differentiating advantage of its in-house developed Kirin SoC chips. However, since May 2019, Huawei has been affected by U.S. sanctions. In September 2020, TSMC, which previously manufactured chips for Huawei, announced the cessation of production. With no supply from TSMC, Huawei’s inventory of 5G chips was depleted by the third quarter of 2022.

Unable to acquire high-end chips, Huawei’s market share in the smartphone industry saw a significant decline. The company could only source 4G chips not subject to U.S. sanctions from Qualcomm or UNISOC. It was believed that U.S. sanctions would severely impact Huawei’s smartphone supply chain and push the company into a dire situation. However, upon analyzing Huawei’s latest release, it is evident that the new smartphone not only features an in-house developed SoC chip by Huawei’s semiconductor subsidiary HiSilicon but also incorporates components and designs from various Chinese manufacturers.

• China’s Semiconductor Self-Sufficiency Continues to Strengthen, Minimal Impact on Taiwanese Supply Chain Expected

China’s pursuit of semiconductor self-sufficiency has become an inevitable outcome of industry development. Although Huawei has not provided detailed specifications for the SoC chip in the Mate 60 Pro, it is speculated that this chip likely uses SMIC’s N+2 process. Due to sanctions, SMIC has been unable to obtain essential EUV equipment. Furthermore, based on the chip’s performance benchmarking, it is comparable to Qualcomm’s flagship Snapdragon 888 chip released in 2021. This suggests that the SoC’s process technology likely falls in the range of 7-14nm, which still lags behind current advanced processes. Nevertheless, this achievement underscores China’s commitment to semiconductor self-sufficiency.

As China gains the ability to independently develop and produce chips, the question arises of whether other Chinese smartphone brands, apart from Huawei, will begin their own chip development efforts. Will this development impact Taiwanese IC design house and foundries that previously held related orders? MediaTek, for instance, primarily supplies chips to brands such as OPPO and vivo. Given that Huawei competes strongly with OPPO and vivo in the smartphone market, it is unlikely that these two brands will entrust their smartphone core SoCs to Huawei’s HiSilicon. Additionally, developing proprietary chips comes with significant costs. Therefore, under these circumstances, it is expected that OPPO and vivo will maintain their partnerships with MediaTek. MediaTek’s chip designs can also utilize TSMC’s advanced processes, giving OPPO and vivo a key competitive advantage against Huawei. Consequently, it is inferred that as long as there is a significant gap between the processes and yields of SMIC and TSMC, Taiwanese foundries will not be significantly affected.

(Photo credit: Huawei)

As applications like AIGC, 8K, AR/MR, and others continue to develop, 3D IC stacking and heterogeneous integration of chiplet have become the primary solutions to meet future high-performance computing demands and extend Moore’s Law.

Major companies like TSMC and Intel have been expanding their investments in heterogeneous integration manufacturing and related research and development in recent years. Additionally, leading EDA company Cadence has taken the industry lead by introducing the “Integrity 3D-IC” platform, an integrated solution for design planning, realization, and system analysis simulation tools, marking a significant step towards 3D chip stacking.

Differences between 2.5D and 3D Packaging

The main difference between 2.5D and 3D packaging technologies lies in the stacking method. 2.5D packaging involves stacking chips one by one on an interposer or connecting them through silicon bridges, primarily used for assembling logic processing chips and high-bandwidth memory. On the other hand, 3D packaging is a technology that vertically stacks chips, mainly targeting high-performance logic chips and SoC manufacturing.

CPU and HBM Stacking Demands

With the rapid development of applications like AIGC, AR/VR, and 8K, it is expected that a significant amount of computational demand will arise, particularly driving the need for parallel computing systems capable of processing big data in a short time. To overcome the bandwidth limitations of DDR SDRAM and further enhance parallel computing performance, the industry has been increasingly adopting High-Bandwidth Memory (HBM). This trend has led to a shift from the traditional “CPU + memory (such as DDR4)” architecture to the “Chip + HBM stacking” 2.5D architecture. With continuous growth in computational demand, the future may see the integration of CPU, GPU, or SoC through 3D stacking.

3D Stacking with HBM Prevails, but CPU Stacking Lags Behind

HBM was introduced in 2013 as a 3D stacked architecture for high-performance SDRAM. Over time, the stacking of multiple layers of HBM has become widespread in packaging, while the stacking of CPUs/GPUs has not seen significant progress.

The main reasons for this disparity can be attributed to three factors: 1. Thermal conduction, 2. Thermal stress, and 3. IC design. First, 3D stacking has historically performed poorly in terms of thermal conduction, which is why it is primarily used in memory stacking, as memory operations generate much less heat than logic operations. As a result, the thermal conduction issues faced by current memory stacking products can be largely disregarded.

Second, thermal stress issues arise from the mismatch in coefficients of thermal expansion (CTE) between materials and the introduction of stress from thinning the chips and introducing metal layers. The complex stress distribution in stacked structures has a significant negative impact on product reliability.

Finally, IC design challenges from a lack of EDA tools, as traditional CAD tools are inadequate for handling 3D design rules. Developers must create their own tools to address process requirements, and the complex design of 3D packaging further increases the design, manufacturing, and testing costs.

How EDA Companies Offer Solutions

Cadence, during the LIVE Taiwan 2023 user annual conference, highlighted its years of effort in developing solutions. They have introduced tools like the Clarity 3D solver, Celsius thermal solver, and Sigrity Signal and Power Integrity, which can address thermal conduction and thermal stress simulation issues. When combined with Cadence’s comprehensive EDA tools, these offerings contribute to the growth of the “Integrity 3D-IC” platform, aiding in the development of 3D IC design.

“3D IC” represents a critical design trend in semiconductor development. However, it presents greater challenges and complexity than other projects. In addition to the challenges in Logic IC design, there is a need for analog and multi-physics simulations. Therefore, cross-platform design tools are indispensable. The tools provided by EDA leader Cadence are expected to strengthen the 3D IC design tool platform, reducing the technological barriers for stacking CPU, GPU, or SoC to enhance chip computing performance.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC)