Ahead of TSMC’s upcoming third-quarter earnings call this Thursday, a report by the Commercial Times gives a heads-up on the foundry giant’s outlook of 3nm orders next year. With NVIDIA and AMD ramping up their next-gen AI accelerators, combined with the strong demand from smartphone chips, orders for TSMC’s 3nm node are set to see a surge in 2025, the report indicates.

According to analysts cited by the report, most flagship smartphone chips are expected to be manufactured with 3nm next year. For instance, Apple’s A19 Pro is said to adopt TSMC’s N3P process, while the Android phones are likely to follow suit.

In terms of the demand from AI accelerators, the report notes that AMD’s MI350 series will likely be manufactured with the 3nm node, which is going to benefit TSMC.

It is worth noting that according to another report by Commercial Times, at Advancing AI 2024 last week, AMD CEO Lisa Su highlighted the company’s close partnership with TSMC, saying that she would be glad to see the CHIPS Act bringing more manufacturing lines back to the U.S.

Sources cited by Commercial Times suggest that for now, AMD has no plans to collaborate with chip makers other than TSMC, and that the company is currently conducting a qualification assessment for chip production at TSMC’s Arizona fab (Fab 21).

On the other hand, Commercial Times indicates that NVIDIA’s orders on TSMC will likely see an increase next year, which would further tighten the foundry giant’s capacity in 3nm and 5nm. NVIDIA’s R-series GPUs are reportedly to be manufactured with TSMC’s 3nm as well, the report notes, but it would not be released until 2026.

TSMC is expected to see strong 3nm demands from other tech giants in 2025 as well. According to the report, Intel is said to outsource most of its Lunar Lake chips to TSMC, while the AI PC chip MediaTek co-develops with NVIDIA is also rumored to be built using the 3nm process. The report states that this chip is expected to debut in the second quarter of next year and enter mass production in the third quarter.

Sources cited by the report note that as clients turn to place orders on 3nm for their latest AI accelerators, foundry capacity will further be strained. Notably, TSMC’s CoWoS packaging reportedly allows interposers reaching 3.3 times for its maximum reticle size to manufacture chips such as NVIDIA’s B200, AMD’s MI300, or Intel’s Gaudi 3, with the number of chips produced on per interposer becoming fewer.

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(Photo credit: TSMC)

After reporting disappointing third-quarter earnings forecast, Samsung’s next move has become the center of market attention. According to a report by Business Korea, to turn the situation around, Samsung may shift its strategy focus to early HBM4 mass production, as well as targeting advanced foundry solutions below 2nm.

A couple of days ago, Samsung warned its third-quarter profit would probably reach 9.1 trillion won, falling short of market expectations. Jeon Young-hyun, the head of Samsung’s Device Solutions (DS) division, issued an unusual public apology in the meantime.

Citing industry sources, Business Korea notes that Samsung’s DS division is expected to post an operating profit of around 5 trillion won (about USD 3.8 billion) for the third quarter, which is reportedly below the market expectation of 6 trillion won. The figure is significantly lower than SK hynix’s projected quarterly operating profit, which is expected to be in the high 6 trillion won range, according to the report.

Samsung May Accelerate HBM4 Progress to Turn the Tide

The series of setbacks have prompted the struggling giant to take action. As Samsung’s lackluster performance could be attributed to its delay in supplying NVIDIA with its 12-layer HBM3e product, industry insiders cited by Business Korea suggest that accelerating the mass production of HBM4, as well as introducing 2nm foundry solutions, could just be the remedies Samsung needs.

In terms of the HBM market, in which Samsung is lagging behind SK hynix on HBM3e verification, the report indicates that Samsung is expected to prioritize the early mass production of HBM4, which is projected to become mainstream in 2025.

A source familiar with the situation told Business Korea that HBM orders from companies other than NVIDIA would rise next year. Major tech firms, including AMD, Amazon, Microsoft, Google, and Qualcomm, are also working on AI semiconductors. Therefore, it does not necessarily mean that Samsung should concentrate solely on NVIDIA, and it could accelerate supply contracts with NVIDIA’s competitors, the report notes.

TrendForce’s latest findings indicate that Samsung, SK hynix, and Micron have all submitted their first HBM3e 12-Hi samples in the first half and third quarter of 2024, respectively, and are currently undergoing validation. SK hynix and Micron are making faster progress and are expected to complete validation by the end of this year.

2nm Advancements Would be Another Focus

On the other hand, in terms of the foundry sector, the report suggests that Samsung is expected to further enhance its ‘turnkey order’ strategy. This approach addresses concerns about technology leakage while providing HBM as part of a comprehensive package.

According to the report, Samsung is set to begin mass production of its GAA 2nm process in 2025. The company also aims to complete the development of the 2nm process with Backside Power Delivery Network (BSPDN) technology by 2027. Having secured 2nm orders from Japan’s AI unicorn Preferred Networks (PFN) and U.S. AI semiconductor company Ambarella, Samsung reportedly plans to seek collaboration with major tech firms.

To attract customers, Samsung will host the “Foundry Forum 2024” online on October 24. Previously scheduled to be held in Beijing, the event will now be conducted virtually, which aligns with the company’s efforts to reduce costs. Will it make further progress in advanced nodes? The whole world is watching.

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(Photo credit: Samsung)

As AMD unveiled the roadmap for its upcoming AI accelerators at Advancing AI 2024, including MI325X and MI355X, its longtime foundry partner TSMC is expected to be the major beneficiary, according to the reports by the Commercial Times and the Economic Daily News.

TSMC, as AMD’s key chip making partner, is expected to benefit the most, as the foundry giant also provides advanced packaging services such chiplets and CoWoS, Commercial Times notes.

Other Taiwanese companies in the supply chain are also expected to benefit, including ASMedia, which provides PCIe Gen5 high-speed interface chips, as well as ASIC firms GUC and Alchip, according to the report. Among server OEM partners, Compal, Wistron, Wiwynn, and Inventec are listed as AMD’s collaborators.

According to the Economic Daily News, AMD’s Instinct MI325X AI accelerator is said to be manufactured with TSMC’s 4nm and 5nm, with mass production anticipated to begin this quarter. It is worth noting that the AI GPU would be the first of its kind to be equipped with 256GB HBM3e memory, according to another report by Wccftech.

On the other hand, to compete with AI chip giant NVIDIA’s GB200, AMD also introduced the MI350 series at the event. According to Commercial Times, MI355X will be launched in the second half of 2025, leveraging TSMC’s 3nm process while equipped with 288GB HBM3e memory.

The report by Commercial Times further notes that in addition to its larger memory capacity, the MI355X accelerator also incorporates the CDNA 4 architecture, allowing it to achieve a significant 35x increase in FP8 computational performance.

Featuring TSMC’s 3nm node just like NVIDIA’s Rubin reportedly does, AMD’s MI355X has the potential to catch up with, or even run ahead of its archrival in terms of product schedule, the report suggests. NVIDIA’s Rubin is reportedly to be released in the fourth quarter of 2025.

Notably, AMD’s MI300X accelerator has been reportedly adopted by a few tech heavyweights. According to Commercial Times, following Microsoft’s adoption, Samsung has also purchased USD 20 million worth of AMD MI300X units for AI training.

At Advancing AI 2024, which took place on October 10^th, AMD also introduced its latest EPYC server processors, EPYC 9005 Series, previously codenamed Turin. According to its press release, the EPYC 9005 Series is built on the latest “Zen 5” architecture, which offers up to 192 cores and will be available in a wide range of platforms from leading OEMs and ODMs. According to the Economic Daily News, EPYC 9005 Series is manufactured with TSMC’s 3nm and 4nm nodes.

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(Photo credit: AMD)

Intel’s first processor using rival TSMC’s technology, the Lunar Lake, has officially launched, intensifying the competition with AMD. According to a recent report by TechNews, third-party testing has confirmed Intel’s claims: Lunar Lake is indeed the most energy-efficient x86 processor to date, outperforming Qualcomm’s Snapdragon X and even rivaling Apple’s M3, reminiscent of Apple’s groundbreaking M1 launch.

TechNews attributes this success not only to Intel’s redesign of power supply, frequency regulation, and packaging but also to the advanced TSMC N3B process.

Recently, Intel announced that in order to reduce costs and better prepare for its in-house 18A process, it has decided to abandon the introduction of the 20A process. As a result, the Arrow Lake chip launching this month will also use TSMC’s process. TechNews raised the question in their article: “With Intel’s new platforms expected to rely on TSMC’s process at least until 2026, will AMD face significant challenges?”

Can AMD’s Zen 5 architecture turn the tide?

TechNews noted that AMD’s current advantage over Intel rests heavily on using TSMC’s process. However, AMD is not alone in benefiting from TSMC’s power efficiency. Across the board, chips produced with TSMC technology have demonstrated superior energy efficiency, delivering high performance without consuming excessive power. But, with the efficiency gains from advanced nodes like M4 or A18 nearing their limits, chipmakers will need to adopt more aggressive power and frequency strategies to push performance further.

Lunar Lake’s impressive energy efficiency highlights both TSMC’s process advantage and Intel’s enduring design prowess. This should serve as a warning for AMD, which plans a major push into the laptop market in 2025. With the launch of Strix Point and Hawk Point this year, AMD aims to release five new platforms next year, targeting the mid-to-high-end laptop market. However, reviews of Strix Point already show that, while performance has improved, energy efficiency remains stagnant—a problem that could persist with future Zen 5-based products.

This opens a window of opportunity for Arrow Lake, which is now powered by TSMC’s process. If Arrow Lake can offer higher peak performance than Raptor Lake Refresh or Meteor Lake while maintaining strong energy efficiency—and with better OEM partnerships—AMD’s hard-earned foothold in the mid-to-high-end market may once again be overshadowed by Intel.

Facing competition shifts due to process changes is nothing new for AMD. As mentioned in the TechNews report, when NVIDIA launched the RTX 30 series on Samsung’s 8LPU (8nm) process, early issues with leakage and high power consumption gave AMD’s RX 6000 series GPUs, known for their superior performance and energy efficiency, a competitive edge. The high-end 6800 and 6900 models were even able to compete with NVIDIA’s RTX 3080. However, once NVIDIA returned to TSMC for the RTX 40 series, AMD struggled to keep up and eventually abandoned its high-end GPU plans, shifting focus to niche markets.

TechNews concludes that while next year may see the lowest degree of processor process diversity—since almost everyone is using TSMC—it will also be a critical year to evaluate the true design strengths of each semiconductor company. With AMD’s Zen 5 already on the table, all eyes are now on Intel’s Arrow Lake to see what surprises it brings to the market with TSMC’s technology.

(Photo credit: AMD)

There are signs that OpenAI, the company that rose to fame with its AI models, is now eyeing the semiconductor manufacturing sector. However, can building a wafer fab be an easy success?

Recently, international media revealed details of OpenAI CEO Sam Altman’s meetings with senior executives from multiple chip manufacturers during his visit to Asia last year.

Altman visited top executives at companies such as TSMC and Samsung, proposing an ambitious plan to invest $7 trillion to build 36 new wafer fabs and data centers to drive the development of artificial intelligence. Altman envisioned that these fabs, funded by the United Arab Emirates, would produce AI chips, which OpenAI and other companies could use to build AI data centers.

The report highlighted that the scale of the investment Altman mentioned is equivalent to a quarter of the annual output of the U.S. economy. To meet OpenAI’s expansion needs for computing power, it would take several years to complete the necessary wafer fabs.

However, due to cost considerations, TSMC did not endorse Altman’s plan. TSMC executives considered Altman’s proposal too aggressive and risky. Even building a few more wafer fabs involves high risk due to the immense capital required, let alone 36 fabs.

How Much Does a Wafer Fab Cost? Hundreds of Billions of Dollars

In recent years, driven by the demand for AI models, the need for chips has surged, and wafer fabs have been expanding rapidly. However, as OpenAI’s experience shows building a wafer fab is no simple task. It faces challenges such as international dynamics, costs, and technological hurdles, with cost being the largest barrier.

The cost of a wafer fab primarily involves land and facility construction, equipment procurement, technology development and intellectual property, as well as operation and maintenance. Land and facility construction take up a significant portion, as a fab requires extensive land for building plants and basic infrastructure such as electricity, water supply, and communication.

On the equipment side, the purchase of lithography machines, etching machines, ion implanters, and thin-film deposition tools is a major expense, especially for advanced lithography machines, which are extremely costly.

Additionally, a wafer fab requires significant research and operational costs, including intellectual property, equipment maintenance, staff training, safety protocols, and environmental management, all of which demand continuous investment from manufacturers.

When all these factors are calculated, the cost of building a wafer fab is extremely high. Moreover, as chip manufacturing processes evolve, the cost of fabs continues to rise. The industry estimates that the cost of a modern fab is in the range of billions of dollars. For example, Intel’s two factories in Arizona are expected to cost $15 billion each, while Samsung’s fab in Taylor, Texas, is projected to cost $25 billion.

Regional Differences in Wafer Fab Costs

It’s also worth noting that the cost of building a wafer fab varies by region. In Asia, for example, due to a well-established supply chain, abundant talent, and policy support, the cost of building a fab is relatively lower. In regions like Europe, the U.S., and the Middle East, however, costs may be higher due to the need to import technology, train talent, and develop a complete supply chain.

(Photo credit: Intel)