To turn adversity around, Intel launched its latest AI accelerator, Gaudi 3, in late September. However, a report by the Economic Daily News indicates that the struggling giant has significantly slashed the chip’s shipment targets by over 30% for next year, which may severely impact orders for its Taiwanese supply chain.

According to the report, the move could be attributed to the Intel’s internal strategy adjustments and the fluctuation of customer demand, which prompts it to cut orders on Taiwanese companies such as TSMC, ASE Technology, and ASIC firm Alchip.

According to industrial sources cited by the report, Intel originally projected to ship 300K to 350K units of Gaudi 3 in 2025. However, the target has now been revised to 200K to 250K units, marking a reduction of more than 30%.

According to the report, after acquiring Israel-based AI chip company Habana Labs in 2019, Intel seems to be relatively conservative about their co-development of the next-gen AI accelerators. Intel’s cautious attitude is evident from its recent moves, such as expediting the conclusion of previous projects like Gaudi 2, as well as lowering the shipment target for Gaudi 3 next year.

Intel declined to comment on the matter, the report notes.

According to industrial sources cited by the report, the adjustment will pose limited impact to TSMC, which manufactures Intel’s Gaudi 3 with its 5nm node. While the demand for the foundry leader’s advanced nodes remains robust, other customers are expected to quickly fill the gap left by Intel.

In terms of IC packaging and testing services provider ASE and its subsidiary SPIL, as they also have a diversified client portfolio, with major tech companies placing orders, the capacity can be swiftly reallocated to minimize the impact, the report suggests.

Nevertheless, for those with smaller scales and a higher client concentration, the impact may be more significant. Taiwanese ASIC firm Alchip, which provides ASIC design services for Intel’s Gaudi 2 and Gaudi 3, therefore, may be more vulnerable to Intel’s potential shipment reduction, according to the report.

Unimicron, which serves as the primary supplier of substrates for Intel’s chips, may also be impacted by the fluctuation of Intel’s orders, the report notes. However, when asked about the potential impact, the company reaffirms its optimistic outlook regarding the second half of 2024, as it expects the demand for AI accelerators and optical modules to be stronger than the first half.

Currently, NVIDIA still holds the throne in the global AI chip market, with rivals such as AMD and Intel eagerly trying to catch up.

Intel’s latest effort, Gaudi 3, boasts 64 Tensor processor cores (TPCs) and eight matrix multiplication engines (MMEs) to accelerate deep neural network computations, and is specifically optimized for large-scale generative AI, according to its press release. It even claims to offer double the performance at the same cost compared to NVIDIA’s H100, the report says.

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(Photo credit: Intel)

While TSMC is making advancements on its 2nm at full throttle, an unexpected risk may be emerging, which might be more severe than most could imagine: power supply. Citing a report by S&P, a report by Wccftech highlights that compared with 2023, the foundry giant’s electricity consumption could nearly triple by 2030, accounting for about 24% of the island’s total electricity usage.

Another report by the Economic Daily News warns that the slow growth in Taiwan’s power generation may pose challenges to TSMC’s chip production, which requires high energy consumption.

Citing the data compiled by a S&P’s report titled “Power Is Increasingly A Credit Risk for TSMC,” Wccftech notes that in 2023, TSMC’s electricity consumption had reached nearly 250 GW, accounting 8% of Taiwan’s total electricity use and almost 16% of the industrial sector’s demand. However, by 2030, TSMC’s share of electricity consumption could soar significantly, contributing 23.7% of the island’s total power usage.

S&P’s calculation is based on the assumption that the TSMC’s wafer shipments will increase by 90% compared to 2023 levels, leading electricity consumption to soar to 794 GW in 2030, Wccftech notes.

It is worth noting that the S&P report, cited by Wccftech, also highlights that extreme ultraviolet (EUV) lithography systems, which are required for processes below 7nm, consume significantly more power than the older deep ultraviolet lithography systems (DUV).

The scenario would weigh heavily on semiconductor heavyweights as they are eagerly pursuing for more advanced nodes. TSMC’s move to 3nm chip production is fueling S&P’s projections of the company’s skyrocketing electricity consumption, Wccftech says.

To put things in context, the report also cites data from Taiwan’s state-owned electricity provider, TaiPower, to show that the island’s electricity reserve margin continues to fall short of the government’s 15% target. While the household electricity consumption continues to decline, TSMC’s power needs, in contrast, keeps growing.

Moreover, according to the Economic Daily News, which also cites S&P’s report, when the electricity reserve margin drops below 10%, the stability of the power supply can be affected.

Citing S&P’s report, the Economic Daily News states that the growth of Taiwan’s power supply is relatively limited. In addition, Taiwan’s policy of replacing cheaper coal and nuclear energy with natural gas and renewable energy will put more pressure on future electricity prices, which may also influence the stability of power supply.

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(Photo credit: TSMC)

Though still be struggling with low yield rates in 3nm, Samsung is reportedly ramping up its efforts to prepare for the mass production of 2nm and 1.4nm to compete with its longtime rival, TSMC. Citing industrial sources on Oct. 3^rd, Business Korea reveals that the South Korean foundry giant is introducing equipment at the Hwaseong plant to establish a 2nm production line, while it also plans to set up a 1.4nm line in its Pyeongtaek 2 plant next year.

According to the report, this initiative is in line with Samsung’s goal to mass produce 2nm in 2025 and 1.4nm by 2027.

In terms of the capacity expansion of 2nm, Samsung aims to install a capacity of 7,000 wafers per month by the first quarter of next year in its S3 foundry line at Hwaseong, Business Korea states. It is worth noting that the existing 3nm line at S3 is expected to be fully converted to a 2nm line by the end of next year.

Then, starting in the second quarter of next year, Samsung plans to set up a 1.4nm production line at the S5 facility in its Pyeongtaek 2 plant, with a capacity of approximately 2,000 to 3,000 wafers per month, according to the report.

Unlike the aggressive expansion for its advanced nodes in South Korea, Samsung’s foundry project in Taylor, Texas, seems to be in stagnant. The company had reportedly planned to begin mass production of below-4nm nodes there by the end of 2024, but this has somehow been pushed back to 2026, which reflects the possible yield issues regarding 3nm node with GAA architecture Samsung has been eager to solve, the report suggests.

Due to a decline in client orders, Samsung’s management has decided to convert the foundry line at its Pyeongtaek 4 plant into DRAM facilities, the report points out. Additionally, the Pyeongtaek 3 plant, which features a 4nm line, has decreased its scale of operation for the same reason.

Analysts cited by the report estimate that Samsung Foundry might incur a deficit of several hundred billion won in the third quarter of this year, underscoring the financial pressures the company is experiencing.

As the delay of the 3nm Exynos seems to be irreversible, securing the success of 2nm has become a top priority for Samsung. Business Korea indicates that the testing of Samsung’s 2nm will be conducted on the next-generation Exynos chip, codenamed “Tethys.” Evaluations may also be said to extend to chips from Qualcomm, Japan’s Preferred Networks (PFN), and Ambarella.

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(Photo credit: Samsung)

As TSMC has reportedly begun trial production of 2nm chips in its Baoshan Plant in Hsinchu, northern Taiwan, the schedule of mass producing 2nm in 2025 remains on track. A report by Commercial Times reveals that the price of 2nm wafers is expected to double compared to 4/5nm, which may exceed USD 30,000 per wafer.

While the yield rates for advanced nodes of Intel and Samsung are rumored to be relatively low, the rising price of 2nm wafers reflects TSMC’s market monopoly as well as its strong pricing power, the report notes.

Citing comments by sources from semiconductor companies, the report states that fabs have invested heavily in advanced processes. For instance, the R&D investment of 3nm may exceed USD 4 billion, with key partners in TSMC’s supply chain, such as Taiwanese IP providers and material suppliers, playing a critical role.

On the other hand, executives from IC design houses cited by the report reveal that even from the perspective of IC design, the R&D cost for advanced nodes remains high. For instance, the development cost for 28nm is approximately USD 50 million, while 16nm may require an investment of USD 100 million. For 5nm, the R&D cost has soared to USD 550 million, if the expenditure on IP licensing, software verification, and design architecture are factored in.

According to the report, foundries have invested even more, with research institutions estimating that R&D expenses for 3nm may range from USD 4 billion to USD 5 billion. Additionally, constructing a 3nm fab is expected to cost at least USD 15 billion to USD 20 billion. All these factors may lead to the high pricing of wafers in the advanced nodes.

Therefore, for a foundry, the development of a new-generation of node involves massive efforts, and needed to be supported by partners in three key sectors: equipment, software (including IP and EDA tools), and materials, the report notes. Once their products have been validated by the foundry, suppliers can usually secure long-term partnership.

With 2nm set to debut in 2025, TSMC’s key suppliers are expected to see explosive profit growth, the report indicates. According to the report, Taiwanese IP firm M31, for example, has already developed IP that supports the 2nm platform for both smartphones and high-performance computing. Likewise, eMemory has disclosed that it is collaborating with leading foundries to develop 2nm.

On the other hand, as 2nm processes require thinner wafers, Taiwan-based materials companies, such as Kinik and Phoenix Silicon International Corp., have entered the markets of diamond discs and reclaimed wafers.

According to the report, in terms of reclaimed wafers, the market value for 2nm is approximately 4.6 times that of 28nm. In addition, the number of dummy wafers will also increase in advanced processes, which benefit suppliers with more volume and higher average prices.

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(Photo credit: TSMC)

Amkor and TSMC announced today that the two companies have signed a memorandum of understanding to collaborate and bring advanced packaging and test capabilities to Arizona, further expanding the region’s semiconductor ecosystem.

Amkor and TSMC have been closely collaborating to deliver high volume, leading-edge technologies for advanced packaging and testing of semiconductors to support critical markets such as high-performance computing and communications. Under the agreement, TSMC will contract turnkey advanced packaging and test services from Amkor in their planned facility in Peoria, Arizona. TSMC will leverage these services to support its customers, particularly those using TSMC’s advanced wafer fabrication facilities in Phoenix. The close collaboration and proximity of TSMC’s front-end fab and Amkor’s back-end facility will accelerate overall product cycle times.

The companies will jointly define the specific packaging technologies, such as TSMC’s Integrated Fan-Out (InFO) and Chip on Wafer on Substrate (CoWoS) that will be employed to address common customers’ needs.

The agreement underscores the shared commitment to supporting customer requirements for geographic flexibility in front-end and back-end manufacturing, as well as fostering the development of a vibrant and comprehensive semiconductor manufacturing ecosystem in the United States. The companies’ shared vision is to enable seamless technology alignment for customers across a global manufacturing network.

“Amkor is proud to collaborate with TSMC to provide seamless integration of silicon manufacturing and packaging processes through an efficient turnkey advanced packaging and test business model in the United States,” said Giel Rutten, Amkor’s president and chief executive officer.

“Our customers are increasingly depending on advanced packaging technologies for their breakthroughs in advanced mobile applications, artificial intelligence and high-performance computing, and TSMC is pleased to work side by side with a trusted longtime strategic partner in Amkor to support them with a more diverse manufacturing footprint,” said Dr. Kevin Zhang, TSMC’s Senior Vice President of Business Development and Global Sales, and Deputy Co-COO.“We look forward to close collaboration with Amkor at their Peoria facility to maximize the value of our fabs in Phoenix and provide more comprehensive services to our customers in the
United States.”

(Photo credit: Amkor)