As TSMC has reportedly begun trial production of 2nm chips in its Baoshan Plant in Hsinchu, northern Taiwan, the schedule of mass producing 2nm in 2025 remains on track. A report by Commercial Times reveals that the price of 2nm wafers is expected to double compared to 4/5nm, which may exceed USD 30,000 per wafer.

While the yield rates for advanced nodes of Intel and Samsung are rumored to be relatively low, the rising price of 2nm wafers reflects TSMC’s market monopoly as well as its strong pricing power, the report notes.

Citing comments by sources from semiconductor companies, the report states that fabs have invested heavily in advanced processes. For instance, the R&D investment of 3nm may exceed USD 4 billion, with key partners in TSMC’s supply chain, such as Taiwanese IP providers and material suppliers, playing a critical role.

On the other hand, executives from IC design houses cited by the report reveal that even from the perspective of IC design, the R&D cost for advanced nodes remains high. For instance, the development cost for 28nm is approximately USD 50 million, while 16nm may require an investment of USD 100 million. For 5nm, the R&D cost has soared to USD 550 million, if the expenditure on IP licensing, software verification, and design architecture are factored in.

According to the report, foundries have invested even more, with research institutions estimating that R&D expenses for 3nm may range from USD 4 billion to USD 5 billion. Additionally, constructing a 3nm fab is expected to cost at least USD 15 billion to USD 20 billion. All these factors may lead to the high pricing of wafers in the advanced nodes.

Therefore, for a foundry, the development of a new-generation of node involves massive efforts, and needed to be supported by partners in three key sectors: equipment, software (including IP and EDA tools), and materials, the report notes. Once their products have been validated by the foundry, suppliers can usually secure long-term partnership.

With 2nm set to debut in 2025, TSMC’s key suppliers are expected to see explosive profit growth, the report indicates. According to the report, Taiwanese IP firm M31, for example, has already developed IP that supports the 2nm platform for both smartphones and high-performance computing. Likewise, eMemory has disclosed that it is collaborating with leading foundries to develop 2nm.

On the other hand, as 2nm processes require thinner wafers, Taiwan-based materials companies, such as Kinik and Phoenix Silicon International Corp., have entered the markets of diamond discs and reclaimed wafers.

According to the report, in terms of reclaimed wafers, the market value for 2nm is approximately 4.6 times that of 28nm. In addition, the number of dummy wafers will also increase in advanced processes, which benefit suppliers with more volume and higher average prices.

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(Photo credit: TSMC)

Amkor and TSMC announced today that the two companies have signed a memorandum of understanding to collaborate and bring advanced packaging and test capabilities to Arizona, further expanding the region’s semiconductor ecosystem.

Amkor and TSMC have been closely collaborating to deliver high volume, leading-edge technologies for advanced packaging and testing of semiconductors to support critical markets such as high-performance computing and communications. Under the agreement, TSMC will contract turnkey advanced packaging and test services from Amkor in their planned facility in Peoria, Arizona. TSMC will leverage these services to support its customers, particularly those using TSMC’s advanced wafer fabrication facilities in Phoenix. The close collaboration and proximity of TSMC’s front-end fab and Amkor’s back-end facility will accelerate overall product cycle times.

The companies will jointly define the specific packaging technologies, such as TSMC’s Integrated Fan-Out (InFO) and Chip on Wafer on Substrate (CoWoS) that will be employed to address common customers’ needs.

The agreement underscores the shared commitment to supporting customer requirements for geographic flexibility in front-end and back-end manufacturing, as well as fostering the development of a vibrant and comprehensive semiconductor manufacturing ecosystem in the United States. The companies’ shared vision is to enable seamless technology alignment for customers across a global manufacturing network.

“Amkor is proud to collaborate with TSMC to provide seamless integration of silicon manufacturing and packaging processes through an efficient turnkey advanced packaging and test business model in the United States,” said Giel Rutten, Amkor’s president and chief executive officer.

“Our customers are increasingly depending on advanced packaging technologies for their breakthroughs in advanced mobile applications, artificial intelligence and high-performance computing, and TSMC is pleased to work side by side with a trusted longtime strategic partner in Amkor to support them with a more diverse manufacturing footprint,” said Dr. Kevin Zhang, TSMC’s Senior Vice President of Business Development and Global Sales, and Deputy Co-COO.“We look forward to close collaboration with Amkor at their Peoria facility to maximize the value of our fabs in Phoenix and provide more comprehensive services to our customers in the
United States.”

(Photo credit: Amkor)

In addition to China, Russia has also made semiconductors one of its major focuses. According to a report by Tom’s Hardware, which cites local media CNews, the country has set aside over 240 billion rubles (USD 2.54 billion) to fund a program aimed at replacing 70% of the foreign chipmaking equipment by 2030.

This effort, according to the reports, includes the launch of 110 R&D projects to reduce reliance on imported wafer fabrication tools and eventually produce chips using 28nm-class process technology. However, it is worth noting that the total investment is 57 times smaller than what Russia plans to spend on defense in its war with Ukraine in 2025 alone, the reports note.

According to the reports, to put things in context, domestic chipmakers like Angstrem and Mikron can produce chips using mature technologies, such as 65nm and 90nm nodes. However, only 12% of the 400 tools used for chip production in the country are currently made locally.

Moreover, sanctions have worsened the situation, which raise the price of essential equipment by 40% to 50% due to the need to smuggle it into Russia, the reports indicate.

Therefore, to address these challenges, Russia’s Ministry of Industry and Trade, along with government-controlled MIET, have developed the initiative, which addresses multiple aspects of chipmaking, including manufacturing tools, raw materials, and electronic design automation (EDA) tools, according to the reports.

However, the report by Tom’s Hardware raises concerns about the feasibility of the initiative, as many of the specific details remain somewhat vague.

For instance, one of the initiative’s key goal is the development of lithography equipment for 350nm and 130nm process technologies, which has a very wide gap in between. Also, Russia intends to manufacture domestic lithography systems capable of handling 65nm and 90nm process technologies. Nevertheless, even this would represent significant progress in the country’s microelectronics production, it would still lag 25 to 28 years behind the industry’s leading edge, the report states.

The surging global demand for AI chips is straining advanced packaging capacity, driving a sharp focus on fan-out panel-level packaging (FOPLP) within Taiwan’s semiconductor industry. According to a report by Commercial Times, major packaging and testing firms such as ASE and Powertech, alongside equipment manufacturers like Gudeng, GPTC, E&R Engineering, Mirle, and analysis firm MAtek, are investing heavily in FOPLP technology.

The rapid development and expanding applications of AI chips have intensified the need for higher chip performance, smaller sizes, better heat dissipation, and lower costs. As emerging applications such as 5G, AIoT, and automotive chips continue to grow, the demand for high-performance, high-power semiconductors has surged. FOPLP technology, which enhances performance while significantly cutting costs and addressing thermal and signal integration issues, is emerging as a key trend in the market.

ASE has been working on panel-level packaging for several years. The company expects its panel-level packaging equipment to be in place by the second quarter of 2025, maintaining a technological edge. On October 2, ASE announced a nearly NT$8 billion purchase of equipment by its subsidiary, SPIL, from companies including Advantest.

Powertech has already moved into wafer-level fan-out packaging and is now shifting toward panel-level fan-out packaging. The company claims that the new technology can increase chip area output by two to three times. It has dedicated its Hsinchu plant to panel-level fan-out packaging and TSV CIS, positioning itself for future growth opportunities.

Equipment manufacturers are also seeking to capitalize on this trend. GPTC, a supplier to major foundries for InFO packaging, is expected to benefit from future FOPLP opportunities due to the similar nature of its equipment. Gudeng Precision is developing panel-level packaging transport boxes, with mass production expected in 2025.

FOPLP combined with TGV drilling is seen as the key to this technology. Analysts cited by Commercial Times highlight that FOPLP+TGV enables higher area utilization and unit capacity, which effectively reduces heterogeneous packaging costs.

E&R Engineering is focusing on drilling, testing, and cutting equipment for glass substrates, primarily supplying panel manufacturers in Taiwan and outsourced assembly and testing providers in Southeast Asia. Mirle has targeted glass substrate transport equipment, while MAtek is leading the market in glass substrate inspection technology.

(Photo credit: ASE)

The competition between Samsung and TSMC has intensified not only in securing international IC design clients but also in the field of South Korean IC design companies. According to a report by ZDNet Korea, major South Korean AI semiconductor fabless companies, which previously used Samsung’s foundry facilities, are now diversifying their manufacturing by using TSMC’s fabs for new chip mass production.

Industry sources cited by ZDNet Korea reveal that FuriosaAI initially used Samsung’s 14nm process for its first-generation chip, “Warboy,” but switched to TSMC’s 5nm process for its second-generation chip, “Renegade.” Notably, Renegade became the first chip in South Korea’s AI semiconductor sector to utilize 2.5D packaging technology with CoWoS and HBM3 memory. FuriosaAI is also planning to use TSMC’s 5nm process for its next-generation chip, “RenegadeS,” set to launch in the fourth quarter.

Similarly, DeepX, after using Samsung’s foundry process, adopted TSMC’s technology for its latest chip development this year. The company’s “DX-V3” system-on-chip (SoC) is being developed using TSMC’s 12nm process, with a target to release samples later this year. DeepX’s earlier chips, the “DX-M1” AI accelerator and “DX-H1” AI server accelerator, were produced using Samsung’s 5nm process, while the “DX-V1” AI SoC solution was made with Samsung’s 28nm process. The “DX-M1” entered mass production last month. ZDNet Korea also reports that DeepX is currently discussing with Samsung the development of next-generation chips using processes more advanced than 5nm.

Another South Korean IC design company, Moblinet, is utilizing both Samsung and TSMC’s foundry services. Its first-generation chip, “Eris,” was manufactured using Samsung’s 14nm process and began mass production in March this year. The second-generation chip, “Regulus,” is being produced using TSMC’s 12nm process and is expected to launch next year after completing testing.

ZDNet Korea also cites industry experts who emphasize that Samsung’s foundry services need to not only focus on attracting large clients but also improve services for smaller fabless companies. Similar to how TSMC grew by nurturing partnerships with small fabless firms, Samsung should bolster its process technology and develop an ecosystem for IP and fabless companies.

According to TrendForce data, TSMC maintained a global foundry market share of 62.3% in the second quarter of this year, while Samsung held an 11.5% share.

Meanwhile, in the race for major international client orders, WCCFTECH reports that Qualcomm is pursuing a dual-sourcing strategy for its Snapdragon 8 Gen 5 chip, partnering with both TSMC and Samsung. Qualcomm has previously attempted this approach, but Samsung’s inconsistent yields thwarted the plan. Qualcomm is now reportedly considering TSMC’s 3nm ‘N3P’ technology for the high-performance variant of the Snapdragon 8 Gen 5, while Samsung’s SF2, also known as 2nm GAA, is expected to be used for a lower-end version.

(Photo credit: TSMC)