TSMC reportedly plans to utilize 12nm and 5nm process nodes in manufacturing the latest HBM4 memory, according to a report by AnandTech. Citing TSMC’s executives, the world’s largest dedicated semiconductor foundry would employ two fabrication processes, N12FFC+ and N5, to integrate HBM4e memory with next-generation AI and HPC processors.

During TSMC’s presentation at its European Technology Symposium 2024, which took place on May 14th, the company revealed new details about the base dies it will produce for HBM4 using advanced logic processes.

According to a senior director of design and technology platform citing by the report, TSMC is currently working with HBM memory partners, including Micron, Samsung and SK Hynix, on advanced nodes targeting HBM4.

Earlier in mid-April, SK Hynix announced that it has signed a memorandum of understanding with TSMC for collaboration to produce next-generation HBM and enhance logic and HBM integration through advanced packaging technology. The company plans to proceed with the development of HBM4, slated to be mass produced from 2026, through this initiative.

N12FFC+, believed to be more cost-effective, is expected to achieve HBM performance, while the N5 base die could offer more logic with significantly lower power.

In the symposium, TSMC stated that its 12FFC+ process is well-suited for HBM4 performance, enabling memory vendors to construct 12-Hi (48 GB) and 16-Hi (64 GB) stacks, with per-stack bandwidth exceeding 2 TB/second. It is also optimizing CoWoS-L and CoWoS-R for HBM4, which utilize over eight layers to support HBM4’s routing of over 2,000 interconnects with proper signal integrity.

These packaging solutions is said to provide interposers that can accommodate up to 8 times the reticle size, providing ample space for as many as 12 HBM4 memory stacks.

In addition, base dies produced with the N5 process will incorporate increased logic density, lower power consumption, and enhanced performance. However, the most significant advantage may lie in the extremely small interconnect pitches achievable with such advanced process technology, ranging from 6 to 9 microns. This capability will enable N5 base dies to be paired with direct bonding, facilitating the 3D stacking of HBM4 directly on top of logic chips. Direct bonding has the potential to significantly enhance memory performance, a crucial enhancement for AI and HPC chips constantly demanding higher memory bandwidth, according to the report.

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• [News] SK Hynix Partners with TSMC to Strengthen HBM Technological Leadership

(Photo credit: TSMC)

TrendForce’s latest findings revealed that as of 2024, Taiwan is expected to lead the global semiconductor foundry capacity in advanced manufacturing processes (including 16/14nm and more advanced technologies) with a 66% market share, followed by Korea (11%), US (10%), and China (9%). However, the semiconductor production capacities of advanced nodes in Taiwan and Korea are projected to decrease to 55% and 8%, respectively, by 2027.

It is worth noting that though semiconductor heavyweights including TSMC, SK Hynix and Samsung keep raising the amount of investments,  Taiwan and Korea, as the two countries holding the highest market share in advanced nodes, are expected to fall in their market shares.

On the other hand, in the US, where the government has been pushing incentives and subsidies more aggressively, its global capacity share in advanced manufacturing processes is expected to jump from 10% in 2024 to 22% in 2027.

Per the overall foundry capacity, Taiwan is expected to hold approximately 44% of global market share as of 2024, followed by China (28%), South Korea (12%), the US (6%), and Japan (2%). The overall trend is expected to be in line with advanced nodes. In contrast, the overall semiconductor production capacities of Taiwan and South Korea are projected to decrease to 40% and 10%, respectively, by 2027.

China, where foundries focus more on expanding mature process capacities and are backed by government subsidies, is projected to perform relatively strong in the overall global market share, growing from 28% in 2024 to 31% in 2027. Its market share of the matured process (including ≥28nm nodes) capacity is expected to rise from 33% in 2024 to 45% in 2027.

According to a report from THE CHOSUN Daily on May 10th, citing forecast from The Semiconductor Industry Association (SIA) and The Boston Consulting Group (BCG), in 2022, Taiwan and Korea held 69% and 31% shares of the production of the most advanced semiconductors below 10 nanometers, while their market share on the advanced nodes may fall to 47% and 9% in 2032, respectively.

The report as mentioned earlier stated that the dramatic decline in South Korea’s semiconductor production share is primarily attributed to key players like Samsung Electronics and SK Hynix, who currently dominate the global advanced semiconductor market alongside TSMC. However, instead of investing in South Korea, they have opted to establish their latest factories in the United States.

The US government announced earlier in April that it would provide up to USD 6.4 billion in subsidies to Samsung for expanding advanced chip production capacity at its Texas plant. In addition, SK Hynix plans to spend $3.87 billion building an advanced packaging plant and research center for artificial intelligence products in Indiana.

(Photo credit: Samsung)

Intel has secured its supply of the new High-NA EUV (high-numerical aperture extreme ultraviolet) lithography equipment from ASML, which the semiconductor heavyweight will allegedly use on its 18A (1.8nm) and 14A (1.4nm) nodes, according to reports from TheElec and Wccftech.

According to sources cited by TheElec, the Dutch fab equipment maker is manufacturing five units of the kit this year, which will all go to Intel, while Samsung and SK Hynix are expected to wait until the second half of 2025 to obtain the aforementioned equipment.

For companies aiming to produce 2-nanometer chips, High-NA EUV lithography equipment may be critical, with each unit priced at over 5 trillion Korean won (approximately US$ 370 million), indicating Intel’s total investment on ASML’s first batch of High-NA EUV kits may amount to US$ 2 billion, according to TheElec and Wccftech.

Intel has confirmed in mid-April that it has received and assembled the industry’s first High-NA EUV lithography system, which is expected to be able to print features up to 1.7x smaller than existing EUV tools. This will enable 2D feature scaling, resulting in up to 2.9x more density.

Compared to 0.33NA EUV, High NA EUV (or 0.55NA EUV) can deliver higher imaging contrast for similar features, which enables less light per exposure, thereby reducing the time required to print each layer and increasing wafer output.

Intel expects to use both 0.33NA EUV and 0.55NA EUV alongside other lithography processes in developing and manufacturing advanced chips, starting with product proof points on Intel 18A in 2025 and continuing into production of Intel 14A.

According to TSMC’s press release in late April, A16, TSMC’s next technology on its roadmap which will combine its Super Power Rail architecture with nanosheet transistors, is scheduled for production in 2026. However, citing Kevin Zhang, TSMC’s senior vice president of business development, Reuters reported that TSMC does not believe it needs to use ASML’s new High-NA EUV lithography tool machines to build the A16 chips.

(Photo credit: ASML)

In a bid to catch up with leading players like TSMC, the South Korean government is said to have approved a national-level initiative aimed at actively promoting the development of advanced chip packaging technologies, according to a report from South Korean media outlet TheElec.

Citing anonymous sources, the report on April 30th indicates that the feasibility of the aforementioned plan has passed the preliminary examination conducted by the Korea Institute of S&T Evaluation and Planning (KISTEP).

According to reports, the preliminary review targeted a national-level project with a value exceeding KRW 50 billion, with direct government sponsorship exceeding KRW 30 billion. Such projects rarely pass the review in one go, but the aforementioned chip packaging case is an exception.

Most of the reviewers at KISTEP have reportedly reached a consensus, recognizing the necessity of the project to catch up with leaders in advanced packaging like Taiwan’s TSMC, making South Korea a frontrunner.

As per TrendForce’s previous report, by 2027, Korea’s share in advanced process capacity is originally expected to reach 11.5%, with room for further growth.

However, the budget for the 7-year project has been reduced from the original KRW 500 billion to KRW 206.8 billion. After passing the preliminary feasibility review, the project is expected to be formally announced later this year (2024) and is scheduled to commence implementation next year.

Cited by the same report from TheElec, a source involved in the project stated that the budget cut was entirely expected, but the project’s single-pass approval is indeed noteworthy, indicating the government’s deep understanding of the importance of chip packaging.

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• [News] South Korean Government Considering Cooperation with U.S. on Semiconductor Equipment Export Controls against China
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(Photo credit: TSMC)

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company’s 2024 North America Technology Symposium.

TSMC debuted the TSMC A16TM technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW™) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

“We are entering an AI-empowered world, where artificial intelligence not only runs in data centers, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”

New technologies introduced at the symposium include:

TSMC A16TM Technology: With TSMC’s industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap.

A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks.

Compared to TSMC’s N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15- 20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.

TSMC NanoFlexTM Innovation for Nanosheet Transistors: TSMC’s upcoming N2 technology will come with TSMC NanoFlex, the company’s next breakthrough in design-technology co optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.

N4C Technology: Bringing TSMC’s advanced techynology to a broader range of of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025.

N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.

CoWoS, SoIC, and System-on-Wafer (SoW): TSMC’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer. At the same time, our System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.

With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude.

TSMC’s first SoW offering, a logic only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

Silicon Photonics Integration: TSMC is developing Compact Universal Photonic Engine (COUPE ) technology to support the explosive growth in data transmission that comes with the AI boom. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

Automotive Advanced Packaging: After introducing the N3AE “Auto Early” process in 2023, TSMC continues to serve our automotive customers’ needs for greater computing power that meets the safety and quality demands of the highway by integrating advanced silicon with advanced packaging.

TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.

(Photo credit: TSMC)