Global Unichip Corp. (GUC), a leading provider of advanced ASIC solutions, announced that its 3nm HBM3E Controller and PHY IP have been adopted by a major cloud service provider and several high-performance computing (HPC) companies. The cutting-edge ASIC is expected to tape out this year, featuring the latest 9.2Gbps HBM3E memory technology.

In the same announcement, GUC highlighted its active collaboration with HBM suppliers like Micron, stating it is developing HBM4 IP for next-generation AI ASICs.

GUC noted that its joint efforts with Micron have demonstrated the ability of GUC’s HBM3E IP to achieve 9.2Gbps with Micron’s HBM3E on both CoWoS-S and CoWoS-R technologies. Test chip results from GUC show successful PI and SI outcomes, with excellent eye margins across temperature and voltage variations at these speeds.

Moreover, when GUC’s HBM3E IP is integrated with Micron’s HBM3E timing parameters, it improves effective bus utilization, further boosting overall system performance.

“We are thrilled to see our HBM3E Controller and PHY IP being integrated in CSP and HPC ASICs.” said Aditya Raina, CMO of GUC. “This adoption underscores the robustness and advantages of our HBM3E solution, which is silicon-proven and validated across multiple advanced technologies and major vendors. We look forward to continuing our support for various applications, including AI, high-performance computing, networking, and automotive.”

“Memory is an integral part of AI servers and foundational to the performance and advancement of data center systems,” said Girish Cherussery, senior director of Micron’s AI Solutions Group. “Micron’s best-in-class memory speeds and energy efficiency greatly benefit the increasing demands of Generative AI workloads, such as large language models like ChatGPT, sustaining the pace of AI growth.”

(Photo credit: GUC)

Recently, several 6-inch production lines have made significant advancements, focusing on third-generation semiconductor materials like silicon carbide (SiC) and gallium oxide (Ga2O3).

NEXIC Successfully Completes First Wafer Batch in Its Fab

On September 21, NEXIC announced that it had successfully completed the first wafer batch in its fab. NEXIC focuses on technological innovation and product development in SiC power devices and power modules, part of the third-generation semiconductors. The fab which located in Jiangyin, Jiangsu Province, China, began construction in August 2023, with equipment installation scheduled for August 2024.

Reports indicate that NEXIC’s 6-inch power semiconductor manufacturing project has a total investment of RMB 2 billion. The products can be widely used in electric vehicles, photovoltaic power generation, rail transit, and 5G communication. Once fully operational, the fab is expected to have an annual production capacity of 1 million wafers.

In June of this year, industry news revealed that NEXIC’s third-generation semiconductor power module R&D and production base project had signed an agreement to settle in Xidong New City, Wuxi, China. This project with a total investment of over RMB 1 billion, focuses on building an automotive-grade third-generation semiconductor power module packaging line, covering applications such as main drive systems, ultra-fast charging piles, photovoltaics, and industrial uses. The project is expected to begin production in 2025, with an annual output of approximately 1.29 million units and an estimated annual output value exceeding RMB 1.5 billion.

China’s First 6-Inch Gallium Oxide Monocrystalline and Epitaxial Wafer Growth Line Breaks Ground

On September 10, Fujia Gallium commenced construction of a 6-inch gallium oxide monocrystalline and epitaxial wafer growth line in Fuyang, Hangzhou.

Founded in 2019, Fujia Gallium is committed to the commercialization of ultra-wide bandgap semiconductor gallium oxide materials, focusing on the growth of gallium oxide monocrystals and the development, production, and sale of gallium oxide substrates and epitaxial wafers. Its products are mainly used in power devices, microwave RF, and optoelectronic detection.

It is reported that Fujia Gallium is currently the only company in China capable of both 6-inch monocrystal growth and epitaxy. This project marks the construction of China’s first 6-inch gallium oxide monocrystalline and epitaxial wafer growth line.

RIR’s 6-Inch Silicon Carbide Device Factory Completed with an Investment of INR 5.1 billion

On September 4, RIR Power Electronics Limited announced the completion of its silicon carbide semiconductor manufacturing plant in Odisha, India, with a total investment of INR 5.1 billion.

RIR is a subsidiary of the U.S.-based Silicon Power Group in India, specializing in the production of power electronic components. RIR’s product portfolio includes low to high-power devices and IGBT modules, serving industries such as energy, transportation, renewable energy, and defense.

In July 2023, Silicon Power Group announced the establishment of the SiC factory in Odisha, India, dedicated to producing 6-inch SiC wafers. The investment was made through its Indian subsidiary, RIR. In October 2023, RIR received approval from the Odisha state government to invest INR 5.108 billion in the project, which is expected to be fully operational by 2025.

In addition to RIR, Chennai-based SiCSem Private Limited announced in June its plans to establish a silicon carbide (SiC) manufacturing, assembly, testing, and packaging (ATMP) plant in Odisha, India.

On June 15, SiCSem signed a cooperation agreement with the Indian Institute of Technology Bhubaneswar (IIT-BBS) to collaborate on research in the compound semiconductor field. Their first joint project aims to localize SiC crystal growth at IIT-BBS, focusing on the mass production of 6-inch and 8-inch SiC wafers, with an estimated investment of INR 450 million (approximately RMB 38 million).

(Photo credit: Fujia Gallium)

According to The Hindu, India, under a transformative partnership with the U.S., is set to establish its first national security semiconductor fabrication plant. This facility will produce chips for military hardware in both nations, as well as for critical telecommunications and electronics networks.

The ambitious project was announced following talks between Prime Minister Narendra Modi and U.S. President Joe Biden in Wilmington on September 21. The two leaders hailed this first-ever India-U.S. semiconductor fabrication collaboration as a “watershed moment,” according to a joint fact sheet.

Based on a report by Bloomberg, the planned India-U.S. semiconductor plant will manufacture infrared, gallium nitride, and silicon carbide semiconductors. In a joint statement, both sides indicated that the India Semiconductor Mission, along with the strategic technology partnership between Bharat Semi, 3rdiTech Inc, and the U.S. Space Force, will provide support for the establishment of the plant.

Meanwhile, Vietnam is also ramping up efforts to develop its semiconductor industry, having set a development blueprint for 2030 with a vision extending through 2050.

As reported by Vietnam Plus, the country plans to capitalize on its geopolitical advantages and labor market strength to selectively attract foreign direct investment (FDI) in the semiconductor sector during the first phase, from 2024 to 2030.

Vietnam aims to become a global hub for semiconductor talent by strengthening its capabilities across the entire supply chain, from research and design to manufacturing, packaging, and testing.

The Vietnamese government has set an ambitious goal of training 50,000 engineers by 2030 to support this high-tech industry. In the second phase, from 2030 to 2040, Vietnam plans to further integrate with global semiconductor and electronics industries, becoming a key global center. By the third phase, from 2040 to 2050, Vietnam aspires to be a global leader in semiconductors and electronics, advancing its research and development capabilities.

By the end of this period, Vietnam aims to build a self-sufficient semiconductor ecosystem, securing a leading position in various steps of the global supply chain.

(Photo credit: Samsung)

A few weeks ago, Intel is said to be seeking assistance from the U.S. government, as CEO Pat Gelsinger reportedly turned to Commerce Secretary Gina Raimondo to emphasize the significance of U.S. chip manufacturing. Now here’s the latest development: according to a report by Bloomberg, the U.S. House has passed a bill that exempts certain semiconductor manufacturing projects from federal permitting requirements, which is expected to benefit companies like Intel and TSMC.

According to Bloomberg, the move aims to alleviate concerns that environmental reviews and legal challenges could slow the construction of domestic chip plants.

The report notes that spurred by incentives from the 2022 Chips and Science Act, chipmakers have committed around USD 400 billion to build factories in the US. Companies such as Intel and TSMC are set to receive billions in funding from the act to support major projects nationwide. Other tech giants, including Micron, Samsung, SK hynix and GlobalFoundries, are also getting billions in U.S. subsidies.

However, many of the projects are facing delays. For instance, Intel’s Fab 52 and Fab 62 in Arizona are previously scheduled to be completed in 2024. However, the schedule may be reportedly delayed a bit, as the fabs are likely to begin operations later this year or in early 2025. The USD 20 billion project in Ohio, on the other hand, may be facing larger obstacles as Intel has delayed the plan after 2026 due to market downturns and delays in U.S. subsidies.

The pending awards, according to Bloomberg, currently require semiconductor construction sites to undergo National Environmental Policy Act (NEPA) reviews, a process that could last months or even years. Now it would be streamlined by the legislation passed on Monday.

The bill specifies three criteria for Chips Act-funded projects to qualify for a NEPA exemption, Bloomberg states.

First, projects must begin construction before the end of this year, a requirement that most major sites should be able to meet, except for a Micron’s project in New York, which has not yet met permitting requirements under the Clean Water Act and various state regulations, Bloomberg explains.

Second, projects that receive only loans—not direct grant funding—would be exempt from NEPA reviews, although this provision currently does not apply to any Chips Act incentive packages.

Finally, facilities would qualify for an exemption if grant funding constitutes less than 10% of project costs, a decrease from the previous threshold of 15% in an earlier version of the legislation, the report notes.

It is worth noting that the proposal, waiting for Biden’s nod, illustrates the dilemma the U.S. government is currently facing. For one thing, the U.S. authority is eager to expedite the construction of chip factories to reduce reliance on Asia, particularly Taiwan. On the other hand, the White House has set ambitious climate goals, and building semiconductor plants could complicate efforts to achieve these targets, according to Bloomberg.

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• [News] Intel Reportedly Sought Commerce Secretary Raimondo’s Help over U.S. Reliance on TSMC

(Photo credit: Intel)

In mid-August, TSMC had signed a contract with panel manufacturer Innolux to purchase its plant and facilities located in southern Taiwan, eyeing to further expand its advanced packaging capacity. According to a report by China Times, the fab, designated as the AP8 facility, is expected to start production in the second half of 2025.

More importantly, the fab will not only provide foundry services but also the eagerly needed capacity for advanced 3D Chip on Wafer on Substrate (CoWoS) IC packaging services, the report notes.

The move will be critical for TSMC to meet the surging demand for the advanced packaging capacity for AI servers, according to the report. Its future capacity will reportedly be nine times that of AP6, TSMC’s advanced packaging fab in Zhunan.

Outbidding Micron, TSMC secured the plant with a transaction value of NTD 17.14 billion, which is much lower than the rumored market price of over NTD 20 billion. Citing sources from the supply chain, the report suggests that the main reason TSMC acquired Innolux’s fab was to bypass the time-consuming environmental assessment process.

Unlike the advanced packaging fab in Chiayi, central Taiwan, which has to be started from scratch, the newly-acquired facility only requires internal modifications. Within a year, TSMC can finish the job of equipment installation, and begin the production afterwards.

Sources cited by the report note that orders for related equipment manufacturing are already underway, with deliveries expected starting in April next year. While the process of trial production may take an additional quarter, the AP8 facility is expected to start production in the second half of 2025.

During an investor conference in mid-April, TSMC Chairman C.C. Wei stated that he anticipates the company’s CoWoS capacity to more than double in both 2024 and 2025. He noted later in July that TSMC targets to reach the balance between supply and demand by 2026.

According to analysts cited by the report, TSMC’s CoWoS capacity, though still remains in short supply, could exceed 32,000 wafers per month by the end of this year. With the additional outsourced capacity, the total CoWoS capacity may approach 40,000 wafers per month. By the end of 2025, TSMC’s CoWoS monthly capacity is projected to reach around 70,000 wafers.

Citing remarks by Jun He, TSMC Vice President of Operations and Advanced Packaging Technology and Service, TSMC’s CoWoS capacity is expected to achieve a compound annual growth rate (CAGR) of over 50% from 2022 to 2026. The foundry giant will also accelerate its pace on constructing fabs, shortening the typical 3-to-5-year timeline to within 2 years to meet customer demand.

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• [News] TSMC Took Another Step in Advanced Process Expansion

(Photo credit: TSMC)