In order to counter the competition from chip rivals such as AMD and NVIDIA, Intel reportedly plans to scale up its outsourcing efforts by handing over to TSMC more 3nm orders for its upcoming Lunar Lake and Arrow Lake chipsets in 2025, according to industrial sources cited by Commercial Times.

TSMC will continue to secure a large volume of outsourced business from IDMs, maintaining a strong cooperative relationship with Intel, acording to the Commercial Times report.

According to the report, Intel aims high for Arrow Lake as the chipset will feature two TPUs (Tensor Processing Units), allowing it to maintain high performance and high clock speeds while reducing power consumption by at least 100 watts. As the result, the product is regarded by Intel as a critical advantage for maintaining its lead in the AI PC market.

Intel’s Arrow Lake, its 15th generation CPU, features significant changes in both architecture and manufacturing process, along with a new name—Core Ultra 200S, according to its press release.

According to the Commercial Times, the processor is not only built using TSMC’s 3nm process, with a substantial reduction in computational core area and energy consumption, but also moving away from the traditional SoC design by adopting Intel’s exclusive 3D Foveros technology.

Foveros, Intel’s 3D advanced packaging technology, is a first-of-its-kind solution that enables the building of processors with compute tiles stacked vertically, rather than side-by-side, according to its press release. The focus of this new design is on energy efficiency, reducing packaging power consumption, and enhancing multi-core performance, the report notes.

According to the supply chain sources cited by the Commercial Times report, the Intel 7-Series chipsets in the 13th and 14th generations, in spite of adopting an 8P+16E (8 Performance-core and 16 Efficient-core) core configuration, the compute tile area still accounted for as much as 70% of the total chip area. However, by switching to TSMC’s 3nm process, the same core configuration now takes up only a third of the total area, while allowing the space for an additional NPU unit.

Though Intel has not given up its foundry unit, the struggling giant does seem to gradually loose competitiveness in advanced nodes, and it has outsourced several products to TSMC. The company’s latest flagship AI processor, Gaudi 3, is fabricated with TSMC’s 5nm.

Recently, in order to reduce costs and better prepare for its in-house 18A process, Intel has decided to abandon the introduction of the 20A node, and leverages TSMC’s process for the Arrow Lake chipset.

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• [News] Intel Impresses the Market with Upbeat Q4 Guidance; 18A to Begin High-Volume Production in 2H25
• [News] Intel Shifts to TSMC for Chip Production: A Looming Threat for AMD?

(Photo credit: Intel)

According to Tom’s Hardware, citing a report from HardwareLuxx, Intel has postponed  its Magdeburg fab project to 2029-2030, raising concerns in Germany about whether the allocated funding should be returned to the federal budget.

The German government took some time to secure €10 billion in funding for Intel’s Fab 29 project near Magdeburg. However, construction has faced multiple delays due to various challenges, including Intel’s worsening financial situation. These issues have ultimately led to a temporary halt in the project, pushing its completion timeline further into the future.

The report from Tom’s Hardware indicates that Intel has decided to delay the project restart until 2029 or 2030. If the project is indeed halted until then, it would severely impact Germany’s semiconductor industry development plans and raise concerns about the future use of the €10 billion in subsidies initially allocated to Intel, including whether these funds should be reallocated.

The report pointed out that, according to the original plan, Intel was expected to receive the first portion of the €10 billion subsidy in 2024, which was approximately €3.96 billion. However, with the project on hold, these funds are now postponed.

The report highlighted that Germany’s Finance Minister, Christian Lindner, has advocated reallocating the subsidy to meet other economic needs, which could help Germany’s finances amid current economic pressures. However, Vice Chancellor and Minister for Economic Affairs Robert Habeck opposes this approach, arguing that the funding should continue to support long-term economic growth and environmental initiatives.

As for whether Intel can soon restart the project, the report indicated that, citing industry sources, given Intel’s current financial difficulties, the probability of the Magdeburg fab project resuming is now less than 50%, and there is a significant chance that Intel may ultimately abandon the project entirely.

Furthermore, the report pointed out that if Intel decides to proceed with the Magdeburg fab, it may need to renegotiate with the German federal government over subsidy details, while given the global economic environment over the next few years, securing large subsidies may be challenging.

On the other hand, if Intel ultimately abandons the Magdeburg fab project, Germany would also face issues related to land use. The report noted that the initial land development was tailored specifically for this facility, which could make it difficult to repurpose the site efficiently in the short term, potentially hindering local economic development plans.
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• [News] Intel’s Plant Delay Casts Doubt on German Economy, with Chances of Proceeding Estimated at No More than 50%
• [News] Intel’s 1nm-class Fabs in Germany Reportedly Delayed Due to Black Soil Concerns and Pending EU Subsidy Approval

(Photo credit: Intel)

According to a report in Commercial Times, the leading Chinese semiconductor foundry, SMIC (Semiconductor Manufacturing International Corporation), released its financial report for the third quarter on the evening of November 7. Due to robust growth in wafer production capacity and sales, SMIC’s revenue in the third quarter increased by 14% sequentially to USD 2.17 billion, a record high, reaching the milestone of USD 2 billion in a single quarter for the first time.

As for the Q4 guidance, however, the forecast is relatively muted. According to its press release, SMIC forecasts a 2% year-over-year increase in revenue for the fourth quarter. The company also expects its gross profit margin for the fourth quarter to be between 18% and 20%.

According to a report in the Reuters, in its third-quarter earnings call, SMIC CEO Zhao Haijun noted that current oversupply conditions are prompting the company to adopt a more cautious approach to capacity expansion. Zhao pointed out that industry utilization rates are around 70%, well below the optimal 85%, reflecting significant overcapacity. He warned that this overcapacity, especially in mature node chips, is likely to persist through 2025, if not worsen. As a result, SMIC was cautious on building new capacity.

In its press release, SMIC reported a 34% increase year-over-year in revenue for the period, reaching USD 2.17 billion. The gross profit was USD 444.2 million, and the gross margin was 20.5%, compared to 13.9% in 2Q24 and 19.8% in 3Q23.

According to Commercial Times, citing Wallstreetcn, SMIC’s financial report indicated that its wafer sales in the third quarter increased by 38% year-over-year to 2.122 million units. Additionally, the company added a monthly production capacity of 21,000 12-inch wafers in the third quarter, further optimizing its product structure and increasing the average selling price.

The Commercial Times report pointed out, citing Wallstreetcn, in terms of revenue composition, the revenue share from 8-inch wafers dropped by 4.5 percentage points from the previous year to 21.5%, while the revenue share for 12-inch wafers reached 78.5%.

According to another report by Reuters, SMIC is primarily known for producing mature node chips for standard electronic devices. However, the company is also involved in manufacturing advanced chips for Huawei’s high-end smartphones, including the Mate 60, launched last August, and the Pura 70 series, released in April.

According to a report from Wccftech, it was rumored that SMIC is able to produce 5nm chips for Huawei this year, without the need for extreme ultraviolet (EUV) lithography machines manufactured by Dutch company ASML, but later it was indicated that Huawei’s next Kirin SoC for the Mate 70 Series will still be limited to the 7nm process but will utilize a more refined “N+3” node, according to another report by Wccftech.

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• [News] Huawei’s Mate 70 Will Reportedly Use a Kirin SoC Made with SMIC’s 7nm Node instead of 5nm
• [News] SMIC Reportedly to Manufacture 5nm Chips for Huawei Without EUV Machinery

Following previous controversies of supplying 7nm chips to Huawei through proxies, TSMC has reportedly notified all its AI chip customers in China by formal emails that starting next week (November 11), it would halt shipments of all the 7nm and more advanced chips to its AI/GPU clients there, according to Chinese media outlet ijiwei.

While this decision may temporarily reduce TSMC’s business in China, in the long run, TSMC could gain more opportunities in the U.S. market by complying with American regulations, the report says.

According to ijiwei’s analysis, TSMC’s move, which highlights the foundry giant’s delicate position in the global semiconductor supply chain amid the heating chip war between the world’s two superpowers, could become a watershed moment in the future of technology development, with long-lasting impacts.

According to the ijiwei report, with the newly elected Trump claiming that TSMC should pay a “protection fee,” the company’s latest move seems to be an effort to align itself with the U.S. Department of Commerce. The two parties, together, have created a stringent review system to completely block advanced process from China’s reach, the report notes.

According to another media outlet SEMICONVoice, the U.S. Department of Commerce has reportedly instructed TSMC to make the move, as production could only proceed after being reviewed and approved by the U.S. Department of Commerce’s BIS (Bureau of Industry and Security) and receiving a license. This would effectively tighten the availability of advanced 7nm and below processes for all Chinese AI chips, GPUs, and autonomous driving ADAS systems, the report notes.

According to the latest report by Bloomberg and Reuters, TSMC has almost finalized binding agreements for multi-billion dollar grants and loans to back its U.S. factories, which may allow it to receive the funding from the Biden administration soon.

TSMC’s package, announced in April, includes USD 6.6 billion in grants and up to USD 5 billion in loans to aid the construction of three semiconductor factories in Arizona.

On the other hand, TSMC’s decision would be a major blow to China’s AI ambition, as AI and GPU companies in China will no longer have access to TSMC’s advanced process, which could lead to higher costs and longer time-to-market, and significantly impact their product performance and market competitiveness, the ijiwei report states.

A supply chain reshuffle is likely to follow, as Chinese chip design companies may need to seek alternative foundries, according to the report.

China’s SMIC, currently the world’s third largest foundry, is said to successfully produce 5nm chips using DUV lithography instead of EUV. However, as previously reported by the Financial Times, industry sources have indicated that SMIC’s prices for 5nm and 7nm processes are 40% to 50% higher than TSMC’s, while the yield less than one-third of TSMC’s.

According to TrendForce, as of the second quarter of 2024, SMIC maintains a solid 5.7% market share, securing its position in third place, after TSMC (62.3%) and Samsung (11.5%).

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• [News] TSMC Reportedly Halts Shipments to Chinese Firm Sophgo After Chip Found in Huawei Processor

(Photo credit: TSMC)

Taiwan’s semiconductor factories operate around the clock, consuming significant amounts of electricity. Taiwan Power Company has raised industrial electricity rates twice this year, and the financial impact is now starting to appear in corporate earnings.

According to Economic Daily News, TSMC Chairman C.C. Wei highlighted in the recent earnings call that Taiwan’s electricity rates have become the highest among regions with wafer fabs. TSMC warned that rising power costs and inflation could reduce its. gross margin by one percentage point. GlobalWafers, a major supplier of semiconductor wafers, also reported lower-than-expected gross margins for Q3, acknowledging energy costs as a key factor.

Wei stated that Taiwan’s electricity rates increased by 14% in October, following hikes of 15% in 2022 and 17% in 2023, with a further 25% increase anticipated in 2024. While TSMC’s third-quarter gross margin surpassed expectations at 57.8%, driven by high capacity utilization, the company projects margins could edge toward 58% this quarter. However, Wei cautioned that surging electricity costs and the costly transition from 5nm to 3nm technology are likely to dampen these gains.

The Economic Daily News report noted that GlobalWafers posted a 30% Q3 gross margin, falling short of market forecasts. Chairman Doris Hsu attributed the shortfall to four main factors: rising electricity costs worldwide, increased depreciation due to investments in multiple plants, declining silicon carbide prices, and changes in product mix, which lowered revenue and margins.

Hsu pointed out that energy is the second-largest production cost for GlobalWafers, comprising 8–9% of total expenses. At the company’s Texas facility, the unit cost of electricity is roughly one-third of Taiwan’s rate. If energy costs remain low and exchange rates are favorable, the gross margin for U.S. plants could slightly exceed that of Asian plants, excluding depreciation differences due to the longer operational history of Asian facilities.

Taiwan Power recently raised industrial rates again in October and announced a carbon fee for 2026. Hsu estimated that a carbon fee of NT$300 per ton could impact Taiwan’s production costs, reducing gross margins by 0.5 to 0.7 percentage points on a consolidated basis.

Establishing production facilities in North America offers logistics advantages by bringing production closer to clients and reducing shipping costs. Hsu explained that transporting a 300mm (12-inch) wafer from Japan to Europe currently costs ¥300, set to rise to ¥550 in November. Shipping to the U.S. would cost even more, but distribution from Texas would significantly reduce these expenses. GlobalWafers’ Texas facility is expected to complete construction by the end of 2024, with mass production slated for late Q1 2025.

TSMC’s first North American wafer fab is expected to begin production in Q1 2025, with two additional fabs set to meet customer demand by 2028 and 2030. Focused on operational efficiency, TSMC aims to leverage AI tools to boost productivity, with each 1% improvement projected to add $1 billion to profits.

(Photo credit: TSMC)