While surrounded by concerns raised by the USD 1.6 billion net loss in Q2 and the large-scale layoff plan, Intel has finally shared some good news. It announced on August 6^th that its next-gen 18A process has achieved a major milestone, and will start production in 2025.

The semiconductor giant states that the milestone has been achieved less than two quarters after tape-out, and confirms that two of its next-gen products, Panther Lake (AI PC client processor) and Clearwater Forest (server processor), will be fabricated with the node. The first external customer is expected to tape out on Intel 18A in the first half of next year, according to its press release.

The company also gives an advance notice on the progress of the aforementioned two processors. According to Intel, Clearwater Forest will mark the industry’s first mass-produced, high-performance solution combining RibbonFET, PowerVia, and Foveros Direct 3D for higher density and power handling. In addition, Panther Lake DDR memory performance is already running at target frequency.

Earlier in July, Intel released the 18A Process Design Kit (PDK) 1.0, design tools that enable foundry customers to harness the capabilities of RibbonFET gate-all-around transistor architecture and PowerVia backside power delivery in their designs on Intel 18A.

It is worth noting that Intel’s 18A is the company’s second fabrication technology, following 20A, to employ RibbonFET and PowerVia. A report by Tom’s Hardware notes that compared to Intel’s 2nm-class node, 18A offers an optimized RibbonFET design and additional enhancements, resulting in a 10% increase in performance per watt, which makes it especially fitted for data center-class products that require significant power.

The report also notes that Intel 18A is a process that Intel Foundry’s potential customers are very interested in, as some believed it to be more competitive than TSMC’s 3nm and 2nm-class offerings, which are expected to be available between 2024 and 2025.

On the other hand, TSMC, the global foundry leader, said earlier in the earnings call that it’s 2nm (N2) node is progressing well, and will begin mass production in 2025. The company is also on track to launch the N2P and A16 processes in the second half of 2026.

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(Photo credit: Intel)

Per a report from Reuters, Intel is said to be receiving the second new High-NA EUV equipment from ASML, costing EUR 350 million (~USD 383 million).

According to Intel’s earnings call on August 1, CEO Pat Gelsinger stated that Intel began receiving the first large equipment in December, and the installation process would take several months, which is expected to bring about a new generation of more powerful computer chip.

Gelsinger noted during the call that the second High-NA equipment is about to enter the facility in Oregon. Due to the poor stock performance following Intel’s earnings report, this statement did not attract much attention.

Previously, a senior executive from ASML once mentioned in July that the company already begun shipping the second High NA equipment to an unnamed customer, but would only record revenue for the first set this year. However, there are still some uncertainties regarding when the customer will adopt this equipment.

ASML has already received orders for over ten High-NA equipment from customers including TSMC, Samsung, Intel, Micron, and SK Hynix. Intel plans to use this technology for mass production by 2027, and TSMC is also set to receive the equipment this year, the time to put into production has not been disclosed, though.

ASML executive Christophe Fouquet stated on July 17 that DRAM memory chip manufacturers, which could refer to Samsung, SK Hynix, or Micron, are expected to start using High-NA equipment by 2025 or 2026.

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(Photo credit: ASML)

According to STDaily citing a recent report on the official website of Okinawa Institute of Science and Technology Graduate University (OIST) in Japan announced that, the university has designed an extreme ultraviolet (EUV) lithography technology that surpasses the standard boundary of semiconductor manufacturing.

Lithography equipment based on such a design can use a smaller EUV light source, consuming less than one-tenth the power of traditional EUV lithography equipment, which can reduce costs and significantly improve the reliability and lifespan of the equipment.

In traditional optical systems, such as camera, telescope, and conventional ultraviolet lithography technologies, optical elements like apertures and lenses are arranged symmetrically along a straight axis. This method is not suitable for EUV rays because their wavelengths are extremely short and most will be absorbed by materials.

Thus, EUV light is guided using crescent-shaped mirrors, but this leads to light deviation from the central axis, sacrificing important optical properties and reducing the overall performance of the system.

To tackle this issue, the new lithography technology achieves its optical properties by aligning two axisymmetric mirrors with tiny central holes in a straight line. Due to the high absorption rate of EUV, each mirror reflection weakens the energy by 40%.

In accordance with industry standards, only about 1% of the EUV light source energy reaches the wafer after passing through 10 mirrors, which requires a very high EUV light output.

In contrast, limiting the number of mirrors from the EUV light source to the wafer to a total of four allows more than 10% of the energy to penetrate the wafer, which can largely bring down power consumption.

The core projector of the new EUV lithography technology, consisting of two mirrors similar to an astronomical telescope, can transfer the light mask image onto the silicon wafer. The team claims this configuration is incredibly simple since traditional projectors require at least six mirrors.

This was achieved by rethinking the theory of optical aberration calibration, and its performance has been verified by optical simulation software, which means it can meet the production requirements of advanced semiconductors.

Besides, the team designed a new type of illumination optical method called “dual-line field” for this novel technology, which uses EUV light to illuminate a plane mirror light mask from the front without interfering with the light path.

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(Photo credit: OIST)

In addition to the strong memory momentum which contributes to Samsung’s soaring profits in the second quarter, the tech giant’s progress on the foundry and chip business also attracts attention. According to its press release on July 31st, Samsung expects its foundry revenue growth to outpace the market in 2024 on the back of the full-scale mass production of second-generation 3nm GAA technology.

Earlier in May, Samsung announced the tape-out of its first 3nm mobile SoC, which used the Synopsys.ai EDA suite to verify the design. It signifies a major milestone as it is the first smartphone AP taped out with its 3nm GAA process. Before that, Samsung’s SF3E node has only been utilized for cryptocurrency mining chips.

The Korean semiconductor heavyweight now notes that the initial response to the new SoC for wearables, which features the industry’s first 3nm technology, has been favorable, and adoption of 3nm SoCs by key customers is expected to expand in the second half of the year. It also plans to ensure a stable supply of the Exynos 2500 for flagship models.

It is worth noting that another focus for Samsung in 2H24 will be the expansion for the application of 200-megapixel sensors from main wide camera to tele cameras. Samsung states it plans to expand sales of DDI products with the start of mass production of new models for a customer based in the US. According to an earlier report by The Verge, Apple may begin using Samsung camera sensors as early as 2026, ending Sony’s decade-long role as the exclusive supplier of the phone’s camera sensors.

Samsung also draws an ambitious roadmap, saying that it will expand its order intake for AI and HPC applications, targeting a fourfold increase in the customer base and a ninefold increase in sales by 2028 from the levels in 2023.

Samsung announced its financial results for the second quarter today, posting KRW 74.07 trillion in consolidated revenue and operating profit of KRW 10.44 trillion (approximately USD 7.5 billion). Its DS Division posted KRW 28.56 trillion in consolidated revenue and KRW 6.45 trillion in operating profit for the second quarter, posting a 94% and 1081% YoY growth, respectively.

Its Foundry Business saw improved earnings as a result of increased demand across applications. Due to higher orders for sub-5nm technology, the number of AI and HPC customers increased twofold from a year earlier. The Foundry Business also distributed the process development kit (PDK) for 2nm Gate-All-Around (GAA) technology to customers ahead of mass production in 2025.

On July 9^th, Samsung confirmed that it has received the first client for its 2nm process, and will provide turnkey semiconductor solutions using the 2nm process and the advanced 2.5D packaging technology Interposer-Cube S (I-Cube S) to Japanese AI company Preferred Networks.

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(Photo credit: Samsung)

TSMC announced last year that it would build a plant in Dresden, Germany. The plant is originally expected to break ground as early as Q4 this year, but now it may start sooner. According to a report from Deutsche Welle, TSMC’s Dresden plant will begin construction within a few weeks, which means it will start this fall, aligning with the company’s previously announced timeline.

The TSMC Germany plant was initially scheduled to begin construction in the second half of 2024 and to start production by late 2027. The new plant is expected to create approximately 2,000 direct high-tech jobs. TSMC will hold a 70% stake in the plant, with Bosch, Infineon, and NXP each holding 10% stakes, and TSMC will operate the facility. The EU and the German government are subsidizing about half of the plant’s investment.

To ensure the plant can commence production smoothly in 2027, the city of Dresden is investing EUR 250 million to build an industrial water supply system and enhance the reliability of the local power grid.

The TSMC Germany plant is expected to use 28/22nm planar CMOS and 16/12nm FinFET process technologies, with a monthly production capacity of approximately 40,000 300mm (12-inch) wafers.

On the other hand, another global semiconductor giant, Intel, was said to have delayed its construction of Fab 29.1 and 29.2 in Magdeburg, Germany, as the new timeline pushed the start of construction to May 2025, according to a report by Tom’s Hardware, citing German media outlet Volksstimme.

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(Photo credit: TSMC)