Recently, after reporting a loss of USD 7 billion in its manufacturing business for 2023, Intel stated that its investment in France and Italy could not be realized for the time being, which is worth several billion euros and can potentially create thousands of jobs. Relevant investment plans for chip plants mentioned above may have been suspended.

Intel noted in a statement, “Investment in France has been paused,” citing “significant changes in economic and market conditions” since 2022.

The company had selected a location southwest of Paris as a new R&D center for artificial intelligence (AI) and high-performance computing (HPC). The center is planned to open by the end of 2024 and will employ 450 people.

Intel added that the “scope” of the project is undergoing adjustment, and France remains a choice for Intel’s future R&D center.

Two years ago, Intel began negotiations with Italy on plans to invest up to EUR 4.5 billion to build a manufacturing plant in the country. This plant would create 1,500 jobs for Intel and 3,500 jobs for suppliers.

When it comes to the status of the Italian plant, Intel said it currently focused on its active manufacturing projects in Ireland, Germany, and Poland. However, Italy’s Minister of Business, Adolfo Urso, stated in March of this year that Intel had delayed its investment in Italy.

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(Photo credit: Intel)

As former U.S. President Trump has brought up the topic that Taiwan should pay for protection, raising concerns on cross-strait issues at the same time, Taiwan’s semiconductor industry and its foundry leader, TSMC, have once again draw market attention. Some scholars believe that the U.S. must realize that Taiwan is not a competitor but an important fabless partner, which could not only play a crucial role in advancing the development of next-gen technologies in the U.S., but help the nation to win the U.S.-China tech battle.

Citing Chien-Huei Wu, a research fellow of the Institute of European and American Studies at Academia Sinica, a report from Technews points out that while profits for foundries have significantly increased in the past five years, it is the IC design sector that gains the largest share of value in the entire supply chain. The benefits to foundries are not particularly significant.

Wu further notes that when NVIDIA, AMD, and Apple place orders, TSMC provides the best service, which indicates that the semiconductor industry in Taiwan is not the only major beneficiary, but U.S. IC companies and the American semiconductor industry as a whole.

U.S. Emerges as the Biggest Winner while Outsourcing Wafer Manufacturing to Taiwan

“The U.S. must recognize that without Taiwan providing better services and designing better processes to overcome limitations, its semiconductor industry would find it difficult to make progress continuously,” said Wu.

Wu believes that the relationship between Taiwan and the U.S. involves high-level cooperation in the supply chain, with each playing its respective role. This is why TSMC founder Morris Chang has repeatedly emphasized that TSMC is a service provider, a trustworthy and reliable partner.

Additionally, the outsourcing of the semiconductor industry is an inevitable trend. Look back in history: the industry had moved from Europe and the U.S. to Japan. Then the Reagan administration sought to suppress the Japanese semiconductor, leading to the signing of the U.S.-Japan Semiconductor Agreement in 1986, while TSMC was founded the following year (1987).

And the history seems to repeat itself. Even after more than forty years, the U.S. has struggled to prevent the industry’s relocation. Now, Taiwan and South Korea have taken the lead in the semiconductor manufacturing business, and there are reasons for this.

Wu further explains that the work cultures between the Europe, the U.S., and Asia are entirely different, and these differences in technology, personnel, and culture will all increase manufacturing costs. Furthermore, these hidden costs will have to be absorbed by American consumers, which will inadvertently increase U.S. inflation. The situation not only harms American consumers but also hinders the country in the competition of next-generation advanced technologies.

The U.S. May be More Concerned about TSMC’s Tech Reaching China than Whether the Wafers are “U.S.-made.”

Currently, the market is concerned that Trump might impose a 10% tariff on all imported products if he takes office. According to Wu, the purpose of the tariff is to protect American manufacturers, making consumers more inclined to choose American-made products at the same price level.

“But the premise is that the quality must be the same, and that there must be existing American manufacturers.” He believes that the U.S. currently lacks manufacturers of equivalent quality, as U.S. tech giants, including Intel, place orders with TSMC, which indicates that the tariff may not have the intended effect. If an additional 10% tariff is imposed, products from major companies like NVIDIA, AMD, and Intel will become more expensive, increasing U.S. inflation, which benefits no one.

If this happens, Wu suggests that TSMC could organize manufacturers into a lobbying group, including key players from both Taiwan and the U.S., to expand the impact of the tariffs to the American semiconductor industry.

Furthermore, he notes that the Taiwanese government must work more closely with the industry, acting as a mediator in times of conflict. With both sides maintaining a unified stance, the government should prioritize industry interests in its communications.

In addition to tariffs, the U.S. government is also very concerned about the share of TSMC’s high-end chips going to China, especially with the escalation of the U.S.-China trade war.

Regarding this, Wu comments that as Taiwan’s current technological controls on the flow of technology to China are still in early stages, it will be difficult to convince the U.S. that it is a reliable partner and service provider. Therefore, the Taiwanese government must enhance its efforts to control the flow of high-tech, talent, products, or intellectual property to China, as there is still significant room for improvement.

How Should Taiwan’s Semiconductor Industry Handle U.S.-China Geopolitical Tensions?

Regarding Trump’s views on cross-strait politics, Wu analyzes that he is different from typical Western politicians, as Trump is known for his transactionalism, unilateralism, and personal connections. Namely, he is more concerned with “What’s in it for me (Trump)?” or “What’s in it for the U.S.?”

From Trump’s perspective, maintaining order is no longer an U.S. obligation. Taiwan must protect its own country with its own efforts, including maintaining a certain defense budget.

Additionally, it is worth watching whether Trump’s chip policies aim to relocate the entire semiconductor supply chain from Taiwan to the U.S. Although this poses practical difficulties and is economically unfeasible, Taiwanese government and the semiconductor industry must prepare for the worst-case scenario, and starts policy planning in advance.

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• [News] With Trump’s Odds of Winning Rising, Concerns Arise on Potential Adjustments in Chip Subsidies
• [News] TSMC Maintains Overseas Expansion Strategy, Unfazed by Geopolitical Disruptions

(Photo credit: TSMC)

TSMC continues to showcase its drive in the advanced packaging market. According to a report from MoneyDJ, TSMC has forecasted that CoWoS will remain in high demand through 2025, with potential for capacity to double in two consecutive years. TSMC is also entering the FOPLP (Fan-Out Panel-Level Packaging) space, a technology that OSATs and panel manufacturers have been developing for years, with a goal to launch it in three years.

TSMC’s stronghold on advanced packaging technologies has raised market concerns that OSATs may see their opportunities diminished as TSMC consolidates its market position.

During its earnings call, TSMC introduced “Foundry 2.0,” a new definition for the semiconductor manufacturing industry. This expanded definition now includes not only foundry services but also packaging, testing, photomask production, and other integrated component manufacturing, excluding memory production. TSMC further stated that this new definition will better reflect the company’s growing market opportunities and that the company will focus solely on cutting-edge back-end technologies.

Under this new definition, TSMC estimates the Foundry 2.0 industry will be nearly USD 250 billion in 2023, up from the previous estimate of USD 115 billion. With this new scope, the industry is expected to grow by 10% annually in 2024. Additionally, TSMC’s market share in Foundry 2.0 (logic semiconductor manufacturing) for 2023 is revised to 28%, with expectations for continued growth in 2024.

The sources cited by the report has pointed out that, observing TSMC’s process advancements, the 3nm process began mass production in 2022, with the 2nm process set for 2025, indicating a lengthening of the development cycle to three years.

Regarding the aforementioned nodes, advanced packaging may help enhance performance, reduce costs, and has the advantage of binding high-end products from top-tier clients. Additionally, the investment required for advanced packaging is significantly smaller compared to frontend technologies, making it a crucial area of focus.

The report continues to note that TSMC currently retains the majority of major CoWoS orders and collaborates with OSATs in the WoS segment. However, TSMC has reportedly yet finalized its CoW segment outsourcing orders.

Meanwhile, AMD and NVIDIA have reportedly turned to Amkor and ASE’s subsidiary, Siliconware, for CoWoS-related products, focusing on cost-sensitive high-performance products. Amkor is expected to supply about 70,000 to 80,000 units annually this year, while Siliconware can provide about 50,000 to 60,000 units.

Additionally, OSATs have been confined to mature IC FOPLP technologies for the past 7-8 years, whereas TSMC has announced it will launch its own FOPLP technology in three years.

TSMC’s planned FOPLP is a rectangular CoWoS-L concept, offering advantages in low unit cost and large-size packaging. However, it faces physical limitations such as issues in coating, spinning, and warping. TSMC, backed by a substantial equipment and materials supply chain, is well-positioned to address these challenges.

As for opportunities for other OSATs, the advanced packaging market is actually vast and can be broadly categorized into flip-chip, fan-out, fan-in, 2.5D/3D, and embedded die packaging.

These technologies can be integrated, and OSATs are not limited to TSMC’s top-tier Info, CoWoS, or SoIC technologies. OSATs can offer more cost-effective advanced packaging solutions compared to fabs, providing competitive alternatives in terms of cost and performance.

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• [News] TSMC Pushes for FOPLP Mass Production by 2027, Reportedly Eyeing on Innolux’s Plant
• [News] TSMC Introduces “Foundry 2.0” to Include Packaging, Testing, Mask making and Others

(Photo credit: TSMC)

As the industry is entering the Angstrom era with semiconductor giants eagerly applying EUV machines to the advanced nodes, more details about Samsung’s 2nm have surfaced. According to the latest report by TheElec, Samsung’s 2nm process will feature 30% more extreme ultraviolet (EUV) layers than the 3nm node.

The report notes that Samsung’s 3nm node has 20 EUV mask layers, while the layers of the 2nm node will be increased to late-20. As the cost of manufacturing rises with the number of EUV mask layers, whether the wafer average selling price of Samsung’s 2nm will significantly increase attracts attention.

According to the report, the South Korean semiconductor giant first implemented EUV technology in its logic process nodes with 7nm in 2018. Since then, Samsung has increased the number of EUV layers or process steps with each subsequent node, moving from 5nm to 3nm. The report also states that Samsung’s 1.4nm process, set to begin production in 2027, is expected to feature over 30 EUV layers.

Meanwhile, Samsung is also using EUV in its DRAM production. For its Gen 6 10nm DRAM, Samsung has implemented up to 7 EUV layers, compared to 5 layers used by SK Hynix, TheElec states.

In comparison, according to an earlier report by AnandTech, TSMC’s standard N3 node includes up to 25 EUV layers. TSMC employs EUV double-patterning on some of these layers to achieve greater logic and SRAM transistor density compared to its N5 node.

It is also worth noting that as EUV layers increase with each node, foundries are vying to secure more EUV machines from ASML. The Dutch lithography equipment giant is said to ship over 70 EUV machines to TSMC in 2024 and 2025 in response to the strong demand of 2nm and 3nm, according to a report by MoneyDJ.

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• [News] Samsung Officially Secures Its First 2nm Order, Making AI Chips for Preferred Networks
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(Photo credit: ASML)

In the Q2 earnings call today (July 18th), TSMC Chairman and CEO C.C. Wei introduced the concept of “Foundry 2.0,” redefining the foundry industry to further include sectors like packaging, testing, mask making, and others, the latest report by Technews noted.

C.C. Wei pointed out that under this new definition, TSMC’s foundry market share was 28% in 2023, and the foundry industry is expected to grow by 10% in 2024, while TSMC’s share will increase further. According to data from TrendForce, under the original definition of foundry, TSMC’s market share was 61.2%.

On the other hand, the semiconductor giant projects the entire semiconductor market, excluding memory, to grow by 10% in 2024.

TSMC’s CFO and spokesperson Wendell Huang explained that the reason for TSMC to propose “Foundry 2.0” is due to the involvement of IDM manufacturers in the foundry market, which has blurred the boundaries of the traditional foundry industry.

Moreover, C.C. Wei highlighted the strong demand for TSMC’s 3nm and 5nm processes. Thanks to the strong demand from AI and smartphones for advanced nodes, Wei believes that 2024 will be a strong year for TSMC. Meanwhile, the company also expects this year’s financial forecast and revenue to increase by 24-26% (mid-20%).

TSMC’s 3nm process accounted for 15% of wafer sales revenue in the second quarter of 2024, while 5nm and 7nm accounted for 35% and 17%, respectively. Overall, revenue from advanced processes (7nm and below) reached 67% of total wafer sales revenue for the quarter.

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• [News] TSMC Projects 7.5% Q3 Revenue Growth, Adjusts Full-Year CAPEX Range
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(Photo credit: TSMC)