Google’s Tensor G4 could mark Samsung’s last mass-produced SoC, as earlier in May, Tensor G5 is reportedly adopting TSMC’s advanced 3nm process. Now here’s the latest development. According to a report by Wccftech, the chip, to be used in Google’s upcoming Pixel 10 lineup, has already reached tape-out, with mass production expected in 2025.

Google’s Tensor G5 would be its first fully self-designed smartphone SoC. Previous Tensor chips, somehow, were modifications from Samsung’s Exynos series, with Samsung being its foundry partner.

The report stated that Google’s decision to collaborate with TSMC is influenced by the Taiwanese semiconductor company’s established reliability in mass-producing wafers using its next-generation nodes.

Before Google, the foundry behemoth has already secured several major clients for its 3nm node. Both Qualcomm and Taiwanese smartphone fabless company MediaTek have reportedly adopted TSMC’s N3E node for their first 3nm chipsets. Apple’s upcoming A18 chips for iPhone 16 models, are said to be manufactured with TSMC’s N3E node as well, according to a report by Commercial Times.

On the other hand, regarding the progress of 3nm, Samsung is still struggling with the low yield rate for its latest Exynos 2500 processors. The company targets to increase the yield rate to over 60% before the product enters mass production, according to a previous report by Korean media outlet ZDNet Korea.

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• [News] Google Reportedly Shifts Orders from Samsung to TSMC for Its Upcoming Tensor G5 in the Pixel 10 Series

(Photo credit: Google)

As artificial intelligence (AI) technology enjoys rapid advances, the demand for AI chips is skyrocketing, driving continuous improvements in advanced packaging and HBM (High Bandwidth Memory) technology, which is expected to benefit the silicon wafer industry.

Recently, Doris Hsu, the Chairperson of GlobalWafers, revealed that HBM memory chips required by AI, such as HBM3 and the upcoming HBM4, need to be stacked on dies, with the number of layers increasing from 12 to 16. Additionally, a layer of base wafer is required underneath the structure, which adds to the consumption of silicon wafers.

Previously, it’s reported that there is a severe global shortage of HBM amid the AI boom, and original manufacturers’ HBM production capacity for this year and next already sold out. They are continuously revving up capital investment and expanding HBM production. According to industry insiders, compared to memory technologies of the same capacity and process like DDR5, the size of wafer for HBM chip has increased by 35-45%. Meanwhile, the complexity of HBM manufacturing processes leads to a yield rate that is 20-30% lower than DDR5, while lower yield rate means that fewer qualified chips can be produced from the same wafer area. These two factors imply that more silicon wafers are needed to meet HBM production demands.

Apart from memory, innovations in advanced packaging technology also conduces to silicon wafer. Hsu mentioned that more polished wafers are required for advanced packaging than before in that packaging has become three-dimensional, and the structure and processes have also changed, which means that some packaging may require twice as many wafers as before. With the releasing of  advanced packaging capacity next year, the number of wafers needed will be even more significant.

As an advanced packaging technology, CoWoS (Chip on Wafer on Substrate) is in vogue currently, with demand overbalancing supply.

As per TrendForce’s survey, NVIDIA’s B series, including GB200, B100, and B200, will consume more CoWoS capacity. TSMC is also increasing its annual CoWoS capacity for 2024, with monthly capacity expected to approach 40k by the end of this year, an over 150% increase compared to 2023. The planned total capacity for 2025 could nearly double, and the demand from NVIDIA is expected to account for more than half.

Industry insiders pointed out that with the development of advanced semiconductor processes in the past, die size reduced and brought down the consumption of wafer. Now, driven by AI, the three-dimensionality of packaging leads to an increase in wafer usage, thereby facilitating the development of the silicon wafer industry. However, it is important to note that while silicon wafer is experiencing a boon, the development of HBM and advanced packaging technologies imposes higher requirements on the quality, flatness, and purity. This will also prompt silicon wafer manufacturers to make corresponding adjustments to cope with the AI trend.

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• HBM3e Production Surge Expected to Make Up 35% of Advanced Process Wafer Input by End of 2024, Says TrendForce

The chip war between the U.S. and China keeps escalating, as China’s new regulation would reportedly take effect soon. This time it has a new target – rare-earth materials. According to the reports from Nikkei and Tom’s Hardware, the new regulation would be effective on October 1, asserting state ownership over its rare-earth materials critical for semiconductor production.

This measure aims to protect national and industrial interests, though it is seen internationally as a strategy in the ongoing trade dispute with the U.S., the reports noted. By prohibiting unauthorized access to or disruption of rare-earth resources by any individual or organization, the regulation signifies the state ownership over crucial rare earth metals like gallium and germanium.

The regulation, with its large scope, encompasses the entire rare-earth element supply chain, including mining, smelting, processing, distribution, and export.

Starting from October, 2022, the U.S. has launched a series of export controls, targeting to limit China’s access to advanced semiconductor technologies, while tech giants including Intel, Qualcomm and NVIDIA are not allowed to ship some of their most cutting-edge chips to China. Now a new development seems to emerge, as the White House is said to consider additional restrictions on China’s access to gate-all-around (GAA) transistor technology as well as high-bandwidth memory (HBM), according to reports from Bloomberg and Tom’s hardware.

China’s latest move may be a reaction to U.S. export regulations on advanced wafer fabrication equipment, the reports stated.

It is worth noting that as of 2023, China accounted for approximately 70% of global rare-earth element production, according to the reports. Particularly in the case of gallium, which is essential for power ICs, China dominates around 94% of global supply.

While the production of high-performance components such as CPUs, GPUs, and memory may not be severely affected, restrictions on gallium nitride (GaN) and gallium arsenide (GaAs) could notably affect power chips, radio frequency amplifiers, LEDs, and other critical applications, the reports said.

On the other hand, China’s upcoming regulation on rare earth metals may have other impacts. The reports noted that gallium and germanium, being not scarce, has been maintained at low price levels in China, which makes mining them elsewhere relatively unprofitable. The new restrictions, therefore, have influenced the prices of these metals, prompting companies in other countries to initiate extraction projects, potentially reducing China’s market dominance in the long run.

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• [News] US Reportedly Mulls to Further Limit China’s Access to GAA Chip Technology and HBM
• [News] Escalating US China Tech War! China Reportedly Tightens Grip on Intel and AMD, Impacting TSMC

As semiconductor companies led by TSMC accelerate their pace for capacity expansion, benefiting the local supply chain, industry electricity consumption has emerged as a tough challenge for Taiwan. According to the latest report by the Economic Daily News, Taiwan can only accommodate 20 more large plants, with the power supply possibly reaching its limit in two years.

As its price of industrial electricity is comparatively lower to international rates, the Taiwan market not only attracts semiconductor companies but also international giants to establish data centers, the report noted. In addition to cloud service providers like AWS, Google, and Microsoft, Apple has recently planned to set up a data center in Taiwan.

Citing engineering companies familiar with high-tech industries, the report indicated that more than 10 new data centers are expected to be constructed in Taiwan. With the recent wave of announcements by semiconductor companies to launch advanced nodes and packaging capacities in Taiwan, it is estimated that once the 2nm and 1.6nm factories are fully operational, approximately 10 more semiconductor plants will result in a power supply challenge.

That is to say, Taiwan could accommodate around 20 more tech plants to be built by 2026 in total, the report said.

Take TSMC as an example. According to earlier reports by Commercial Times, the foundry giant’s 3nm plant in Tainan plans to begin mass production in the third quarter, while EUV (Extreme Ultraviolet Lithography) machines will be introduced progressively at another 3nm plant, P8 in Hsinchu, next year. On the other hand, TSMC’s advanced 2-nanometer process capacity is set to begin mass production in 2025.

Commercial Times noted that the EUV machines, crucial for advanced processes, will see over 60 units delivered this year and next to TSMC.

However, EUV machines are considered “electricity-consuming monsters.” According to an earlier report by BITS&CHIPS, ASML’s EUV machine consumes about a megawatt to produce 160 wafers per hour. Since a chip must go through twenty passes in this scanner, this results in an additional energy consumption of about 0.2 kWh per square centimeter of the chip, totaling 1.6 kWh per square centimeter. An earlier report by Bloomberg estimated that because of the vast amount of power needed to run EUVs, TSMC is expected to use 12.5% of Taiwan’s entire electricity supply by 2025.

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• [News] TSMC Achieved a New Step in the Construction of its Third 2nm Fab
• [News] TSMC Reportedly Invests over USD 12.3 Billion in EUV, Advancing in 2nm Production

(Photo credit: TSMC’s P8, DACIN Construction)

Recently, TSMC reportedly got approval for the land change and environmental assessment of its third 2nm plant in Kaohsiung.

It is reported that the Nanzih Industrial Park in Kaohsiung City will adapt to the changing needs of the global semiconductor industry supply chain and will carry out the development of the park in stages. TSMC obtained the construction permit for the first phase of its 2nm advanced process plant in the Nanzih Industrial Park in September 2022, kick starting the construction of first phase, with mass production expected in 2025. The second phase of the plant is also underway.

In response to the shift in the supply chain and the market demand of the global semiconductor industry, TSMC has an urgent need to expand production. The Urban Development Bureau of Kaohsiung City Government stated that TSMC chose to initiate the urban plan variation procedure for the third phase of the plant on the east side of the first phase of the park, covering an area of 17.22 hectares.

To ensure that the industrial use category matches the land use content, the special industrial zone will be changed to a Type A industrial zone, and the building coverage ratio will be adjusted to 45% in consideration of the need of construction, while the original floor area ratio of the special industrial zone will remain at 160%.

Regarding the third 2nm plant, the Kaohsiung City Government’s Water Conservancy Bureau issued a statement saying that the city government fully supports TSMC’s establishment of the plant in the Nanzih Industrial Park, and the reclaimed water supply will be fully guaranteed.

As for electricity, the Economic Development Bureau explained that Kaohsiung’s total power generation in 2022 was 50.886 billion kWh, with total electricity sales of 30.734 billion kWh, accounting for only 60% of power generation. In the future, all TSMC plants will adopt a dual-circuit system to ensure stable power supply.

Previously, Tai-Hsiang Liao, Director of the Economic Development Bureau, pointed out in early April that the city government will provide relevant assistance to meet TSMC’s water and electricity supply needs in Kaohsiung. Additionally, Liao further stated that, based on the current land assessment in the park, the maximum scale of TSMC’s Kaohsiung plant could be up to five plants.

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• [News] TSMC Reportedly Invests over USD 12.3 Billion in EUV, Advancing in 2nm Production
• [News] TSMC Reportedly Accelerates 2nm Progress, with Kaohsiung Plant Rumored to Commence First Tool-in by Year-end

(Photo credit: TSMC)