According to TechNews, Taiwan’s semiconductor foundry, PSMC (Powerchip Semiconductor Manufacturing Corporation) recently announced its collaboration with Tata Electronics in India to establish the country’s first 12-inch wafer fabrication plant in Dholera, Gujarat. In an interview on the 4th, Chairman Frank Huang stated that Powerchip’s role primarily involves technology transfer, rather than financial investment, with Tata Group’s wafer plant expected to break ground on March 12.

Huang disclosed that the initiative is 70% funded by the Indian government, which had actively sought Taiwanese semiconductor firms to assist in India. This partnership with India will see PSMC aiding in the plant’s construction, while the operational responsibilities will wholly fall under India’s purview.

Following the agreement between the two parties on February 6, the groundbreaking ceremony, to be presided over by the President of India, is scheduled for this month on the 12th, with Huang himself attending.

Furthermore, Huang mentioned three major projects by the Indian government, including the collaboration between PSMC and Tata, support for Micron Technology’s manufacturing presence in India, and a back-end packaging initiative. Through PSMC’s assistance, the Tata Group plans to produce power management ICs, display drivers, microcontrollers, and high-performance computing logic chips at the 12-inch wafer facility, targeting automotive, computing and data storage, wireless communication, and artificial intelligence application markets.

(Image: PSMC)

In 2023, “generative AI” was undeniably the hottest term in the tech industry.

The launch of the generative application ChatGPT by OpenAI has sparked a frenzy in the market, prompting various tech giants to join the race.

As per a report from TechNews, currently, NVIDIA dominates the market by providing AI accelerators, but this has led to a shortage of their AI accelerators in the market. Even OpenAI intends to develop its own chips to avoid being constrained by tight supply chains.

On the other hand, due to restrictions arising from the US-China tech war, while NVIDIA has offered reduced versions of its products to Chinese clients, recent reports suggest that these reduced versions are not favored by Chinese customers.

Instead, Chinese firms are turning to Huawei for assistance or simultaneously developing their own chips, expected to keep pace with the continued advancement of large-scale language models.

In the current wave of AI development, NVIDIA undoubtedly stands as the frontrunner in AI computing power. Its A100/H100 series chips have secured orders from top clients worldwide in the AI market.

As per analyst Stacy Rasgon from the Wall Street investment bank Bernstein Research, the cost of each query using ChatGPT is approximately USD 0.04. If ChatGPT queries were to scale to one-tenth of Google’s search volume, the initial deployment would require approximately USD 48.1 billion worth of GPUs for computation, with an annual requirement of about USD 16 billion worth of chips to sustain operations, along with a similar amount for related chips to execute tasks.

Therefore, whether to reduce costs, decrease overreliance on NVIDIA, or even enhance bargaining power further, global tech giants have initiated plans to develop their own AI accelerators.

Per reports by technology media The Information, citing industry sources, six global tech giants, including Microsoft, OpenAI, Tesla, Google, Amazon, and Meta, are all investing in developing their own AI accelerator chips. These companies are expected to compete with NVIDIA’s flagship H100 AI accelerator chips.

Progress of Global Companies’ In-house Chip Development

• Microsoft

Rumors surrounding Microsoft’s in-house AI chip development have never ceased.

At the annual Microsoft Ignite 2023 conference, the company finally unveiled the Azure Maia 100 AI chip for data centers and the Azure Cobalt 100 cloud computing processor. In fact, rumors of Microsoft developing an AI-specific chip have been circulating since 2019, aimed at powering large language models.

The Azure Maia 100, introduced at the conference, is an AI accelerator chip designed for tasks such as running OpenAI models, ChatGPT, Bing, GitHub Copilot, and other AI workloads.

According to Microsoft, the Azure Maia 100 is the first-generation product in the series, manufactured using a 5-nanometer process. The Azure Cobalt is an Arm-based cloud computing processor equipped with 128 computing cores, offering a 40% performance improvement compared to several generations of Azure Arm chips. It provides support for services such as Microsoft Teams and Azure SQL. Both chips are produced by TSMC, and Microsoft is already designing the second generation.

• Open AI

OpenAI is also exploring the production of in-house AI accelerator chips and has begun evaluating potential acquisition targets. According to earlier reports from Reuters citing industry sources, OpenAI has been discussing various solutions to address the shortage of AI chips since at least 2022.

Although OpenAI has not made a final decision, options to address the shortage of AI chips include developing their own AI chips or further collaborating with chip manufacturers like NVIDIA.

OpenAI has not provided an official comment on this matter at the moment.

• Tesla

Electric car manufacturer Tesla is also actively involved in the development of AI accelerator chips. Tesla primarily focuses on the demand for autonomous driving and has introduced two AI chips to date: the Full Self-Driving (FSD) chip and the Dojo D1 chip.

The FSD chip is used in Tesla vehicles’ autonomous driving systems, while the Dojo D1 chip is employed in Tesla’s supercomputers. It serves as a general-purpose CPU, constructing AI training chips to power the Dojo system.

• Google

Google began secretly developing a chip focused on AI machine learning algorithms as early as 2013 and deployed it in its internal cloud computing data centers to replace NVIDIA’s GPUs.

The custom chip, called the Tensor Processing Unit (TPU), was unveiled in 2016. It is designed to execute large-scale matrix operations for deep learning models used in natural language processing, computer vision, and recommendation systems.

In fact, Google had already constructed the TPU v4 AI chip in its data centers by 2020. However, it wasn’t until April 2023 that technical details of the chip were publicly disclosed.

• Amazon

As for Amazon Web Services (AWS), the cloud computing service provider under Amazon, it has been a pioneer in developing its own chips since the introduction of the Nitro1 chip in 2013. AWS has since developed three product lines of in-house chips, including network chips, server chips, and AI machine learning chips.

Among them, AWS’s lineup of self-developed AI chips includes the inference chip Inferentia and the training chip Trainium.

On the other hand, AWS unveiled the Inferentia 2 (Inf2) in early 2023, specifically designed for artificial intelligence. It triples computational performance while increasing accelerator total memory by a quarter.

It supports distributed inference through direct ultra-high-speed connections between chips and can handle up to 175 billion parameters, making it the most powerful in-house manufacturer in today’s AI chip market.

• Meta

Meanwhile, Meta, until 2022, continued using CPUs and custom-designed chipsets tailored for accelerating AI algorithms to execute its AI tasks.

However, due to the inefficiency of CPUs compared to GPUs in executing AI tasks, Meta scrapped its plans for a large-scale rollout of custom-designed chips in 2022. Instead, it opted to purchase NVIDIA GPUs worth billions of dollars.

Still, amidst the surge of other major players developing in-house AI accelerator chips, Meta has also ventured into internal chip development.

On May 19, 2023, Meta further unveiled its AI training and inference chip project. The chip boasts a power consumption of only 25 watts, which is 1/20th of the power consumption of comparable products from NVIDIA. It utilizes the RISC-V open-source architecture. According to market reports, the chip will also be produced using TSMC’s 7-nanometer manufacturing process.

China’s Progress on In-House Chip Development

China’s journey in developing in-house chips presents a different picture. In October last year, the United States expanded its ban on selling AI chips to China.

Although NVIDIA promptly tailored new chips for the Chinese market to comply with US export regulations, recent reports suggest that major Chinese cloud computing clients such as Alibaba and Tencent are less inclined to purchase the downgraded H20 chips. Instead, they have begun shifting their orders to domestic suppliers, including Huawei.

This shift in strategy indicates a growing reliance on domestically developed chips from Chinese companies by transferring some orders for advanced semiconductors to China.

TrendForce indicates that currently about 80% of high-end AI chips purchased by Chinese cloud operators are from NVIDIA, but this figure may decrease to 50% to 60% over the next five years.

If the United States continues to strengthen chip controls in the future, it could potentially exert additional pressure on NVIDIA’s sales in China.

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(Photo credit: NVIDIA)

With the flourishing development of technologies such as AI, cloud computing, big data analytics, and mobile computing, modern society has an increasingly high demand for computing power.

Moreover, with the advancement beyond 3 nanometers, wafer sizes have encountered scaling limitations and manufacturing costs have increased. Therefore, besides continuing to develop advanced processes, the semiconductor industry is also exploring other ways to maintain chip size while ensuring high efficiency.

The concept of “heterogeneous integration” has become a contemporary focus, leading to the transition of chips from single-layer to advanced packaging with multiple layers stacked together.

The term “CoWoS” can be broken down into the following definitions: “Cow” stands for “Chip-on-Wafer,” referring to the stacking of chips, while “WoS” stands for “Wafer-on-Substrate,” which involves stacking chips on a substrate.

Therefore, “CoWoS” collectively refers to stacking chips and packaging them onto a substrate. This approach reduces the space required for chips and offers benefits in reducing power consumption and costs.

Among these, CoWoS can be further divided into 2.5D horizontal stacking (most famously exemplified by TSMC’s CoWoS) and 3D vertical stacking versions. In these configurations, various processor and memory modules are stacked layer by layer to create chiplets. Because its primary application lies in advanced processes, it is also referred to as advanced packaging.

According to TrendForce’s data, it has provided insights into the heat of the AI chip market. In 2023, shipments of AI servers (including those equipped with GPU, FPGA, ASIC, etc.) reached nearly 1.2 million units, a 38.4% increase from 2022, accounting for nearly 9% of the overall server shipments.

Looking ahead to 2026, the proportion is expected to reach 15%, with a compound annual growth rate (CAGR) of AI server shipments from 2022 to 2026 reaching 22%.

Due to the advanced packaging requirements of AI chips, TSMC’s 2.5D advanced packaging CoWoS technology is currently the primary technology used for AI chips.

GPUs, in particular, utilize higher specifications of HBM, which require the integration of core dies using 2.5D advanced packaging technology. The initial stage of chip stacking in CoWoS packaging, known as Chip on Wafer (CoW), primarily undergoes manufacturing at the fab using a 65-nanometer process. Following this, through-silicon via (TSV) is carried out, and the finalized products are stacked and packaged onto the substrate, known as Wafer on Substrate (WoS).

As a result, the production capacity of CoWoS packaging technology has become a significant bottleneck in AI chip output over the past year, and it remains a key factor in whether AI chip demand can be met in 2024. Foreign analysts have previously pointed out that NVIDIA is currently the largest customer of TSMC’s 2.5D advanced packaging CoWoS technology.

This includes NVIDIA’s H100 GPU, which utilizes TSMC’s 4-nanometer advanced process, as well as the A100 GPU, which uses TSMC’s 7-nanometer process, both of which are packaged using CoWoS technology. As a result, NVIDIA’s chips account for 40% to 50% of TSMC’s CoWoS packaging capacity. This is also why the high demand for NVIDIA chips has led to tight capacity for TSMC’s CoWoS packaging.

TSMC’s Expansion Plans Expected to Ease Tight Supply Situation in 2024

During the earnings call held in July 2023, TSMC announced its plans to double the CoWoS capacity, indicating that the supply-demand imbalance in the market could be alleviated by the end of 2024.

Subsequently, in late July 2023, TSMC announced an investment of nearly NTD 90 billion (roughly USD 2.87 billion) to establish an advanced packaging fab in the Tongluo Science Park, with the construction expected to be completed by the end of 2026 and mass production scheduled for the second or third quarter of 2027.

In addition, during the earnings call on January 18, 2024, TSMC’s CFO, Wendell Huang, emphasized that TSMC would continue its expansion of advanced processes in 2024. Therefore, it is estimated that 10% of the total capital expenditure for the year will be allocated towards expanding capacity in advanced packaging, testing, photomasks, and other areas.

In fact, NVIDIA’s CFO, Colette Kress, stated during an investor conference that the key process of CoWoS advanced packaging has been developed and certified with other suppliers. Kress further anticipated that supply would gradually increase over the coming quarters.

Regarding this, J.P. Morgan, an investment firm, pointed out that the bottleneck in CoWoS capacity is primarily due to the supply-demand gap in the interposer. This is because the TSV process is complex, and expanding capacity requires more high-precision equipment. However, the long lead time for high-precision equipment, coupled with the need for regular cleaning and inspection of existing equipment, has resulted in supply shortages.

Apart from TSMC’s dominance in the CoWoS advanced packaging market, other Taiwanese companies such as UMC, ASE Technology Holding, and Powertek Technology are also gradually entering the CoWoS advanced packaging market.

Among them, UMC expressed during an investor conference in late July 2023 that it is accelerating the deployment of silicon interposer technology and capacity to meet customer needs in the 2.5D advanced packaging sector.

UMC Expands Interposer Capacity; ASE Pushes Forward with VIPack Advanced Packaging Platform

UMC emphasizes that it is the world’s first foundry to offer an open system solution for silicon interposer manufacturing. Through this open system collaboration (UMC+OSAT), UMC can provide a fully validated supply chain for rapid mass production implementation.

On the other hand, in terms of shipment volume, ASE Group currently holds approximately a 32% market share in the global Outsourced Semiconductor Assembly and Test (OSAT) industry and accounts for over 50% of the OSAT shipment volume in Taiwan. Its subsidiary, ASE Semiconductor, also notes the recent focus on CoWoS packaging technology. ASE Group has been strategically positioning itself in advanced packaging, working closely with TSMC as a key partner.

ASE underscores the significance of its VIPack advanced packaging platform, designed to provide vertical interconnect integration solutions. VIPack represents the next generation of 3D heterogeneous integration architecture.

Leveraging advanced redistribution layer (RDL) processes, embedded integration, and 2.5D/3D packaging technologies, VIPack enables customers to integrate multiple chips into a single package, unlocking unprecedented innovation in various applications.

Powertech Technology Seeks Collaboration with Foundries; Winbond Electronics Offers Heterogeneous Integration Packaging Technology

In addition, the OSAT player Powertech Technology is actively expanding its presence in advanced packaging for logic chips and AI applications.

The collaboration between Powertech and Winbond is expected to offer customers various options for CoWoS advanced packaging, indicating that CoWoS-related advanced packaging products could be available as early as the second half of 2024.

Winbond Electronics emphasizes that the collaboration project will involve Winbond Electronics providing CUBE (Customized Ultra-High Bandwidth Element) DRAM, as well as customized silicon interposers and integrated decoupling capacitors, among other advanced technologies. These will be complemented by Powertech Technology’s 2.5D and 3D packaging services.

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(Photo credit: TSMC)

The competition for dominance in 2nm semiconductor technology has intensified at the beginning of 2024, marking a crucial battleground among global foundry companies.

As per a report from IJIWEI, major foundry enterprises such as Samsung Electronics, TSMC, and Intel are set to commence mass production adopting 2nm process starting this year. Consequently, the fierce competition for supremacy in 2nm technology is expected to escalate from 2025 onwards. Currently, the most advanced production technology globally is at the 3nm level.

• TSMC

TSMC’s 2nm products will be manufactured at the Fab 20 in the Hsinchu Science Park in northern Taiwan and at a plant in Kaohsiung.

The Fab 20 facility is expected to begin receiving related equipment for 2nm production as early as April, with plans to transition to GAA (Gate-All-Around) technology from FinFET for 2nm mass production by 2025.

During TSMC’s earnings call on January 18th, TSMC revealed that its capital expenditure for this year is expected to fall between USD 28 billion and 32 billion, with the majority (70% to 80%) allocated to advanced processes. This figure is similar to that of 2023 (USD 30.4 billion), indicating stable investment to ensure its leading position in 2nm technology.

• Intel

After announcing its re-entry into the foundry business, Intel is actively advancing its foundry construction efforts. The plan includes the introduction of the Intel 20A (equivalent to 2nm) process in the first half of 2024 and the Intel 18A (1.8nm) process in the second half of the year. It is understood that the Intel 18A process will commence test production as early as the first quarter of this year.

Intel’s 2nm roadmap is more ambitious than originally anticipated, being accelerated by over six months. In response to criticisms of its “overly ambitious” plans, Intel swiftly began procuring advanced Extreme Ultraviolet (EUV) equipment.

• Samsung Electronics

Samsung Electronics has devised a strategy to gain an advantage in the more advanced process war through its Gate-All-Around (GAA) technology. Currently, it is mass-producing the first-generation 3nm process based on GAA (SF3E) and plans to commence mass production of the second-generation 3nm process this year, significantly enhancing performance and power efficiency.

Regarding the 2nm process, per a report from Nikkei, Samsung plans to start mass production for mobile devices in 2025 (SF2) and gradually expand to high-performance computing (HPC) in 2026 and automotive processes in 2027.

Currently, Samsung Electronics is producing GAA products for the 3nm process at its Hwaseong plant and plans to manufacture products for both the 3nm and 2nm processes at its Pyeongtaek facility in the future.

• Rapidus

Rapidus, a chip manufacturing company supported by the Japanese government, is expected to trial-adopt 2nm process at its new plant by 2025 and begin mass production from 2027.

If Rapidus’ technology is validated, the global foundry market may expand beyond the Taiwan-Korea duopoly to include Taiwan, Korea, the United States, and Japan.

The technology competition to become a “game-changer” ultimately depends on the competition for customers. It’s rumored that TSMC holds a leading position in the 2nm field, with Apple speculated to be its first customer for the 2nm process. Graphics processing giant NVIDIA is also considered a major customer within TSMC’s client base.

According to TrendForce data as of the third quarter of 2023, TSMC’s revenue share accounted for a dominant 57.9%, with Samsung Electronics trailing at 12.4%, a gap of 45.5 percentage points.

However, Samsung Electronics is not sitting idly by. With continuous technological investment, Samsung’s foundry customer base grew to over 100 in 2022, a 2.4-fold increase from 2017. The company aims to expand this number to around 200 by 2028.

Particularly, Samsung’s early adoption of GAA technology is expected to give it an advantage in achieving early production volumes for advanced processes.

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(Photo credit: TSMC)

The U.S. Department of Commerce has initiated the “National Advanced Packaging Manufacturing Program (NAPMP) ,” with materials and substrates being the first subsidized areas. Due to the close collaboration between IC testing and IC substrates, it is not ruled out that the IC substrate industry could be the next recipient of subsidies under the U.S. chip legislation.

However, according to Commercial Times’ report, there is a lack of interest among Taiwanese PCB manufacturers in establishing facilities in the U.S., and there are three main reasons for this. 

Firstly, the PCB industry thrives on economies of scale, and the production costs in the U.S. are too high. Taiwanese manufacturers have recently responded to the China Plus One Strategy by establishing facilities in Southeast Asia, making it unlikely for them to set up operations in the U.S.

Secondly, the U.S. is not particularly welcoming to polluting industries, making pure substrate manufacturers more likely candidates. 

Thirdly, domestic PCB manufacturers in the U.S. are also relocating their production lines. If seeking a partnership is necessary, Japanese manufacturers may present a more viable option.

As for potential subsidy recipients, industry experts speculate that one of the more likely beneficiaries could be TTM Technologies, a major PCB manufacturer in the United States. TTM announced in 2023 the establishment of a new facility in the state of New York dedicated to producing HDI PCBs, primarily for military applications in line with U.S. strategic requirements.

The United States plans to invest USD 3 billion in three main areas: an advanced packaging piloting facility, workforce training programs, and funding for projects. The funding is derived from the CHIPS and Science Act, and detailed information on the subsidy program is expected to be announced in early 2024.

In response to this news, the Taiwan Printed Circuit Association pointed out that the conditions for subsidies under the CHIPS and Science Act are stringent. In the past year, the semiconductor supply chain-related companies, led by foundry outsourcing, have started to establish a production presence in the U.S. This includes not only foundries such as TSMC, Samsung, and Intel but also packaging and testing facilities like Amkor and ASE Group.

The association highlighted that IC substrates are part of the semiconductor supply chain, but the more immediate impact is on packaging and testing facilities. If global packaging and testing facilities also take concrete actions to establish operations in the U.S. following the “whole chip” production mindset, the pressure on IC substrate manufacturing will undoubtedly increase. It is not ruled out that the IC substrate industry could be the next focus of the U.S. government’s attention.

While the production scale of IC substrates (or the overall PCB) in the U.S. may not be significant, once categorized as a strategic material, even small-scale production becomes meaningful.

In other words, establishing operations in the U.S. is not solely about scale but rather about companies having the “capability” to produce locally. Reportedly, the industry should pay attention to the future developments in U.S. policy in this regard.

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(Photo credit: iStock)