According to a report from Taiwan’s Economic Daily, TSMC’s 3-nanometer technology has attracted another heavyweight client. Following Apple and MediaTek, it is rumored that Qualcomm will also commission TSMC to produce its next-generation 5G flagship chip using the 3-nanometer process. The chip is expected to be unveiled in late October, making Qualcomm the third client for TSMC’s 3-nanometer technology.

In response to these rumors, Qualcomm has not provided any comments, while TSMC has chosen to remain silent. Industry experts speculate that TSMC’s 3-nanometer technology will likely attract additional orders from major players such as NVIDIA and AMD in the future. With various leading-edge fabs continuously seeking TSMC’s services, it appears that TSMC’s 3-nanometer technology remains the top choice for international giants.

Last year, Qualcomm unveiled its annual 5G flagship chip, the “Snapdragon 8 Gen 2,” manufactured using TSMC’s 4-nanometer process. The previous-generation Snapdragon “8 Gen 1” was produced using Samsung’s 4-nanometer process, but it encountered issues related to heat dissipation. Consequently, Qualcomm released an upgraded version, the “Snapdragon 8+ Gen 1,” using TSMC’s 4-nanometer process.

Qualcomm has traditionally adopted a multi-supplier strategy for semiconductor manufacturing. It is rumored in the industry that Qualcomm has privately informed its smartphone brand customers about the upcoming next-generation 5G flagship chip, the “Snapdragon 8 Gen 3,” expected to be announced in late October. This chip will be available in two process versions: TSMC’s 4-nanometer (N4P) and 3-nanometer (N3E).

(Photo credit: TSMC)

According to Taiwan’s Money DJ, the AI wave is showing no signs of slowing down. Led by NVIDIA, major players including AMD, Intel, and international chip giants are aggressively entering the AI arena, driving increasing demand for advanced packaging and advanced processes. Industry reports suggest that TSMC is reallocating several thousand personnel from its Hsinchu 12B plant to support its Longtan and Tainan 18B facilities in a bid to address the current urgent demands.

TSMC typically follows a process of initial research and development (R&D) stages for advancing its processes before handing them over to the mini-line teams and then proceeding to full-scale production. As a result, the 2nm process is slated for trial production in the second quarter of 2024, leaving a gap of approximately six months. It is rumored that TSMC is mobilizing staff from its Hsinchu 12B plant to provide support for the CoWoS-focused Longtan facility and the Tainan 18B plant, which is responsible for mass-producing the 3nm process, to address the immediate needs.

Equipment suppliers estimate that TSMC’s CoWoS production capacity is set to reach 12,000 to 14,000 wafers per month by the end of this year, with a projected doubling of production by 2024. By the end of that year, it is expected to reach at least 26,000 wafers per month, potentially even surpassing 30,000 wafers. Meanwhile, for the 3nm family, in addition to Apple and MediaTek, AMD, NVIDIA, Qualcomm, and even Intel are confirmed to adopt the N3 family of processes.

(Photo credit: TSMC)

According to a report by Taiwan’s Money DJ, there’s good news from TSMC regarding its 3nm node. Sources within the supply chain have disclosed that the number of new chip designs using the 3nm process, known as “New Tape-Outs” (NTOs), has surged. It’s confirmed that customers including MediaTek, AMD, NVIDIA, and Qualcomm will follow in Apple’s footsteps for mass adoption of the 3nm process in the next year (2024) and the subsequent year. By the second half of next year, the monthly production capacity for the 3nm family, including N3E, will increase from the current approximately 60,000 wafers to 100,000 wafers.

According to publicly available information from TSMC, the company began volume production of its first 3nm process node, N3, in the second half of last year. The enhanced version of the 3nm process, N3E, started production in the latter half of this year. There will also be extensions to the 3nm process, including N3P, N3S, and N3X. This year, Apple’s high-end A17 Pro chip for its iPhones was based on the initial N3 process.

Both TSMC and MediaTek previously announced their collaboration, with MediaTek developing new Dimensity products using TSMC’s 3nm process. The design phase, known as “Tape Out,” has been successfully completed, and mass production is scheduled for next year. Industry reports indicate that aside from Apple and MediaTek, AMD, NVIDIA, and Qualcomm are also confirmed to adopt the N3 family of processes. Intel is also on the list, with mass production planned for the year after next.

TSMC’s first-generation 3nm process currently has a monthly production capacity of about 60,000 wafers, serving Apple as its primary customer. TSMC has initiated a program known as “Continuous Improvement Plan” (CIP) for the 3nm process, referred to as N3B in the industry. Supply chain sources suggest that N3B’s capacity will be integrated into subsequent extended process nodes, such as N3E, which is expected to attract more customers. It is estimated that the overall 3nm monthly production capacity will reach 100,000 wafers by the second half of next year.

(Photo credit: TSMC)

According to a report by Taiwan’s Economic Daily, TSMC is aggressively expanding its advanced packaging capacity. Recently, they placed an additional 30% order for equipment with manufacturers, leading to a doubling of order volumes for companies in the interposer supply chain, such as UMC and ASE Group. Moreover, there are rumors of price increases on the horizon.

TSMC, responding to the robust production demands from major clients like NVIDIA, AMD, and Amazon, has not only expanded its CoWoS capacity as originally planned but has also added another 30% in new equipment. This move implies that once TSMC’s new advanced packaging capacity comes online next year, it will represent at least a doubling of the current production capacity.

Given the substantial demand for TSMC’s advanced packaging orders, coupled with the necessity of interposer in CoWoS for stacking logic computing ICs and high-bandwidth memory, there is an expectation of significant growth in interposer orders, likely exceeding a twofold increase compared to this year. Notably, semiconductor giants like UMC and ASE Group have already secured significant orders from TSMC for interposer layers and are currently in the mass production and delivery stages.

It is understood that UMC, after venturing into the advanced packaging market in recent years, has introduced packaging solutions applicable to IoT, automotive chips, and more, spanning from wafer bumping and wire bonding packaging to advanced 2.5D, 3DIC, and wafer-level fan-out packaging solutions. The most notable among them is the 2.5D silicon interposer layer solution, which, through collaboration with UMC and other specialized packaging facilities, has proven pivotal in securing major orders in the interposer layer market, particularly from NVIDIA.

Industry sources suggest that UMC has increased prices for super hot run interposer layer orders and initiated capacity expansion plans to meet customer demands, while ASE Group is also contemplating adjustments to its advanced packaging quotations.

(Photo credit: UMC)

According to a report by Taiwan’s Economic Daily, TSMC’s CoWoS advanced packaging capacity is running at full throttle. As they actively expand their production capabilities, there are reports of major customers like NVIDIA increasing their orders for AI chips. Additionally, industry giants like AMD and Amazon have rushed in with urgent orders.

In response to this urgent situation, TSMC is actively seeking equipment suppliers to expand its CoWoS machine procurement. Beyond TSMC’s existing production expansion goals, the company is further increasing its orders for equipment by an additional 30%, highlighting the ongoing fervor in the AI market.

It is reported that TSMC has sought assistance from equipment manufacturers such as Scientech, Allring, Grand Process Technology, E&R Engineering, and GP Group for this endeavor. They plan to complete the delivery and installation of the equipment by the first half of the coming year. The related equipment manufacturers are experiencing a surge in activity.

Industry sources reveal that TSMC’s CoWoS advanced packaging monthly production capacity is currently around 12,000 units. With their previous expansion efforts, they aimed to gradually increase this to 15,000 to 20,000 units per month. Now, with the addition of more equipment, they are looking at the possibility of reaching capacities of over 25,000 units per month, potentially even approaching 30,000 units. This substantial increase in production capacity positions TSMC to handle a significantly larger volume of AI-related orders.

Equipment providers have pointed out that NVIDIA is currently TSMC’s largest customer for CoWoS advanced packaging, accounting for 60% of the production capacity. Recently, in response to robust demand in AI computing, NVIDIA has increased its orders. Additionally, urgent orders from other customers such as AMD, Amazon, and Broadcom have started to pour in.

(Photo credit: TSMC)