According to Taiwan’s Economic Daily News, UMC has recently engaged in discussions with global giants such as Texas Instruments and Infineon about long-term cooperation plans. Additionally, Taiwan’s two leading IC design companies, MediaTek and Realtek, have seen their inventories of WiFi 6/6E chips depleted, prompting them to increase their orders with UMC.

TrendForce recently reported that the White House announced on May 14th the imposition of additional tariffs on semiconductor products manufactured in China. This move has accelerated a shift in supply chain orders, leading Taiwanese foundries to receive increased orders, boosting capacity utilization beyond expectations.

For the second half of this year, Vanguard’s capacity utilization is expected to rise above 75%, PSMC’s 12-inch capacity utilization will reach 85-90%, and UMC’s overall capacity utilization will settle between 70-75%.

UMC’s orders from overseas clients are largely driven by the U.S. tariffs on Chinese semiconductor imports, which are projected to double to 50% by 2025. This has spurred a wave of supply chain relocations, with UMC leveraging its diverse manufacturing footprint to attract long-term cooperation plans from companies like Texas Instruments, Infineon, and Microchip.

From the perspective of Taiwanese market, UMC has benefited from a recent recovery in the networking sector. Taiwan’s top two WiFi 6 chip suppliers, MediaTek and Realtek, responding to customer restocking demands, have begun to increase their orders for WiFi chips with UMC.

Recent revenue data from Realtek indicates a rebound in the networking market. In April, Realtek’s consolidated revenue reached NT$10.068 billion, a 11.4% increase month-over-month and a 21.9% increase year-over-year, marking the first time in 20 months that monthly revenue has surpassed NT$10 billion.

MediaTek’s consolidated revenue in April was NT$42.028 billion, a 16.74% decrease month-over-month, yet still the second highest on record for the period, with a 48.25% year-over-year increase. Foundry sources indicate that MediaTek has placed additional orders for the third quarter, suggesting that networking customers are set to upgrade specifications this year.

UMC’s consolidated revenue in April was NT$19.741 billion, up 8.67% month-over-month and 6.93% year-over-year, reaching a 16-month high. UMC previously projected that as inventories in the computer, consumer, and communication sectors return to healthier levels, overall wafer shipments would see a slight increase this quarter. However, in the automotive and industrial sectors, slower-than-expected inventory digestion has kept demand subdued.

(Photo credit: UMC)

This May, we have witnessed two different approaches to the new High-NA EUV (high-numerical aperture extreme ultraviolet) lithography equipment between semiconductor giants. Intel has secured the first batch of High-NA EUV kits from ASML, which will allegedly be used on its 18A (1.8nm) and 14A (1.4nm) nodes. On the other hand, TSMC stated that the company will not utilize this new lithography technology in its upcoming A16 (1.6nm) process.

High-NA EUV machines may be critical for companies aiming to produce chips beyond 2nm, but are they must-have?

Looking back in history, the industry used to believe that when the U.S. prevented EUV exports to China, the act would limit China’s progress in 7nm. However, China’s largest foundry, SMIC, is rumored to produce 5-nm chips for Huawei this year, without the need for EUV lithography machines.

When examining TSMC’s trajectory on EUV itself, it is worth mentioning that the company took a more cautious stance, as well. When Samsung began using EUV in its 7nm process in 2018, TSMC successfully launched its first 7nm production line using mature DUV lithography.

It was not until the stability and maturity of EUV had been confirmed that TSMC started to use EUV in its N7+ process, which took place in 2019. In the end, in spite of Samsung’s early adoption of EUV, yield issues allowed TSMC to overtake them.

Similarly, in the race for the 3nm process, unlike Samsung, instead of rushing to adopt GAAFET, TSMC chose the reliable FinFET route.

Will history repeat itself? Now it would be a good timing to examine TSMC’s strategy on High-NA EUV machines.

High-NA EUV technology: A Cure for All?

According to a report by China’s Jiwei, at the recent 2024 North America Technology Symposium hosted by TSMC, the company revealed that its A16 process would not require the next-generation High-NA EUV lithography machines, with mass production expected in 2026.

An expert cited by Jiwei stated that TSMC’s decision might be due to the higher risk associated with High-NA lithography machines.

The report noted that there would be still quite a few challenges to be resolved, such as supporting light sources for photon shot noise and productivity requirements, solutions for the 0.55 NA’s small depth of focus, computational lithography capabilities, mask manufacturing, and computing infrastructure including new materials. Not to mention there is the necessary debugging and development time to ensure stability, which implies considerable time and hidden costs.

On the other hand, TSMC began to adopt EUV in its N7+ process in 2019, implying the world’s largest chipmaker has committed plenty of time and effort to refine the technology.

According to the report by Jiwei, by optimizing the EUV exposure dose and the photoresist used, as well as improving photomask life, increasing yield, and reducing defect rates, TSMC has achieved significant advancements. Today, the number of EUV lithography machines has increased tenfold, while wafer output nowadays is 30 times that of 2019.

Weigh Between Cost and Technology

In addition to potential technology bottlenecks, higher cost may be another problem. Per a report from Bloomberg, TSMC’s Senior Vice President of Business Development and Co-Chief Operating Officer, Dr. Kevin Zhang, remarked that while he appreciates the capabilities of High-NA EUV, he finds its price tag to be unlikeable.

As per the same report from Bloomberg, ASML’s new High-NA EUV machine is priced at EUR 350 million (roughly USD 380 million). Jiwei further stated the unit price may more than double, comparing with the current EUV machines (roughly EUR 170 million).

Market demand would be another major concern. Citing an industry insider, Jiwei analyzed that the cost of manufacturing chips with High-NA lithography machines increases significantly. While more chips can be cut from each wafer, more chips need to be sold to recoup the investment.

The report stated that the smartphone AP chip market alone cannot absorb these cost without the supporting demand of AI chips. However, as China, the largest market for AI, is now being restricted by export control measures from the U.S., the overall market demand remain uncertain.

Adoption Timing for High-NA EUV? TSMC May Not Be in a Hurry

Then what would be the right timing for TSMC to adopt High-NA EUV?

The report by Jimwei took the trajectory of EUV as an example. When the industry generally regarded EUV essential in the 7nm node, TSMC successfully launched its first 7nm production line using mature DUV lithography. This strategy allowed TSMC to avoid the imperfections and high costs of EUV lithography at that time.

TSMC waited until 2019 to start the usage of EUV in its N7+ process when the technology has become mature enough. In the end, in spite of Samsung’s early adoption of EUV, yield issues allowed TSMC to win the favor of clients.

Similarly, in the race for the 3nm process, instead of rushing to adopt GAAFET, TSMC chose the reliable FinFET route. Despite Samsung’s early lead with 3nm, their low yields and repeated delays enabled TSMC to surpass them.

TSMC’s previously announced roadmap indicates that the 1.4nm A14 process is expected to be introduced between 2027 and 2028, while the development of the 1nm A10 process is projected to be completed before 2030. The report by Jiwei suggested that TSMC might consider using the next-generation lithography machine only after the 1nm process is in place, potentially adopting the High-NA EUV system around 2029 to 2030.

Read more

• [News] How Costly is the High-NA EUV? TSMC Reportedly Shocked, Considering Not Using the Equipment in its A16 Nodes
• [News] Intel to Adopt New High-NA EUV, High Costs Could Lead to Increased Losses

(Photo credit: ASML)

Belgium-based IMEC Microelectronics Research Center has announced the leading role in establishing the NanoIC pilot line project, for which it has received a total of EUR 2.5 billion from public and corporate donations.

As one of the four advanced semiconductor pilot line projects designated by the European Chips Joint Undertaking (Chips JU), the NanoIC pilot line is to bridge the technology gap between the lab and the fab, accelerating the development, design, and testing of proof-of-concept products through small-scale production.

According to the European Chips Act, which has a total budget of EUR 15.8 billion by 2030, the “European Chips Initiative” is regarded as a key part. This initiative aims to significantly enhance advanced chip technologies and innovation. The European Chips Initiative will gather EU, member states, and resources from the stakeholders from third-party countries related to EU programs, which is expected to be driven by the Chips Joint Undertaking (Chips JU).

In addition to spearheading the NanoIC pilot line project, IMEC will also be a part of two other projects: the advanced FD-SOI process pilot line and the advanced heterogeneous system integration pilot line. The NanoIC pilot line will focus on developing sub-2nm process SoC, providing prototype development PDK to participants from academia to industry, thereby reducing the risk of chip R&D and improving development efficiency.

Of the EUR 2.5 billion in funding, EUR 1.4 billion comes from Chips JU and the Belgian government, while the remaining EUR 1.1 billion comes from partners such as  ASML. IMEC President and CEO Luc Van den hove stated that the support from the EU, the Belgian government, and corporate partners will enable IMEC to maintain a top position and better align with market demands.

This investment will double output and learning speed, accelerate the pace of innovation, strengthen the European chip ecosystem, and hence promote economic growth in Europe.

Read more

• [News] Silicon Wafer Long-Term Contracts Unstable, Major Foundry Seeks Price Cut from Japanese Suppliers

(Photo credit: IMEC)

As the demands for AI and HPC processors keep their momentum, driving the usage of advanced packaging technologies, TSMC revealed plans to further expand its chip-on-wafer-on-substrate (CoWoS) capacity at a compound annual rate (CAGR) of over 60% until at least 2026, according to a report by AnandTech.

According to its latest roadmap revealed at the company’s European Technology Symposium earlier, TSMC would now be able to more than quadruple its CoWoS capacity from 2023 levels by the end of 2026, the report indicated.

Last year, the foundry leader announced plans to more than double its CoWoS capacity by the end of 2024, but now it needs to be more ambitious, not only to meet existing demand but also address the future market.

TSMC is also preparing additional versions of CoWoS (specifically CoWoS-L) to support building system-in-packages (SiPs) with up to eight reticle sizes, just in case that increasing CoWoS capacity four-fold over three years may still be insufficient, the report said.

In addition to CoWoS, TSMC also plans to expand its system-on-integrated chips (SoIC) capacity at a CAGR of 100% through 2026, indicating that its SoIC capacity will increase eight-fold from 2023 levels by the end of 2026, according to AnandTech.

When it comes to the latest overseas expansion plans regarding major Taiwanese foundries, TSMC’s Kumamoto Fab 1, a joint investment between TSMC, Sony Semiconductor Solutions Corporation, and Denso Corporation, was inaugurated in February. Construction of the second Kumamoto fab is slated to begin by the end of 2024, with operations starting by the end of 2027.

UMC, Taiwan’s second-largest wafer foundry, announced on May 21st the arrival of the first equipment tools for phase 3 expansion at its Fab12i located in Singapore. According to a report by CNA, UMC anticipates the construction of the facility will be completed by mid-year. However, due to adjustments in customer orders, mass production has been delayed by six months to early 2026.

In October, 2023, Powerchip Semiconductor Manufacturing Corporation (PSMC), in collaboration with SBI Holdings, Inc., announced plans regarding its first semiconductor wafer plant in Japan, which is expected to be located in the Second Northern Sendai Central Industrial Park in Ohira Village, Kurokawa District, Miyagi Prefecture (Second Northern Sendai Central Industrial Park).

Previous reports indicated that PSMC plans to construct multiple plants, with the first phase potentially starting construction as early as 2024, involving an investment of around JPY 400 billion (USD 2.6 billion).

Read more

• [News] TSMC Reportedly Prepares Next-generation HBM4 Manufacturing, Utilizing 12nm and 5nm Process Nodes
• [News] TSMC’s Kumamoto Plant – Semiconductor Bubble or Once-in-a-Century Opportunity?

(Photo credit: TSMC)

According to reports from Korean news outlet FN News and Wccftech, aiming to win back NVDIA as a major customer, Samsung has made it a priority to secure chip order from the GPU heavyweight this year. To achieve this, Samsung is reportedly doing everything possible to ensure the company’s 3nm process node, which uses GAA (Gate-All-Around) architecture, meets NVIDIA’s requirements.

Sources quoted by the reports indicated that Samsung has implemented an internal strategy called “Nemo,” specifically targeting NVIDIA. Its foundry now plans to commence mass production of the 3nm GAA process in the first half of 2024. The GAA technology is expected to overcome significant bottlenecks associated with the previous FinFET processes, but it is still uncertain if this will be sufficient to persuade NVIDIA.

NVIDIA has been cooperating with TSMC in advanced process nodes for developing its GPUs for quite a while, both in consumer and data center markets. The tech giant’s latest GPU families, including Ada Lovelace, Hopper, and Blackwell, are all manufactured using TSMC’s 5nm (4N) processes, according to the aforementioned reports.

It’s important to note that NVIDIA last used Samsung’s 8nm process for its GeForce RTX 30 “Ampere” GPUs, designed for the gaming segment. However, the successor to Ampere, the Ada Lovelace “GeForce RTX 40,” switched to TSMC’s 5nm process.

Considering the high demand for NVIDIA’s GPUs, the chipmaker is expected to procure chips from multiple semiconductor fabs, which is simliar to its previous strategy of dual-sourcing HBM and packaging materials, according to Wccftech.

(Photo credit: Samsung)