As Apple keeps advancing in AI as well as developing its own in-house processors, industry sources indicated that the tech giant’s Chief Operating Officer (COO) Jeff Williams recently made a visit to TSMC, and was personally received by TSMC’s President, C.C. Wei, according a report by Economic Daily News.

The low-profile visit was made to secure TSMC’s advanced manufacturing capacity, potentially 2nm process, booked for Apple’s in-house AI-chips, according to the report.

Apple has been collaborating with TSMC for many years on the A-series processors used in iPhones. In recent years, Apple initiated the long-term Apple Silicon project, creating the M-series processors for MacBook and iPad, with Williams playing a key role. Thus, his recent visit to Taiwan has garnered significant industry attention.

Apple did not respond to the rumor. TSMC, on the other hand, has maintained its usual stance, not commenting on market speculations related to specific customers.

According to an earlier report from The Wallstreet Journal, Apple has been working closely with TSMC to design and produce its own AI chips tailored for data centers in the primary stage. It is suggested that Apple’s server chips may focus on executing AI models, particularly in AI inference, rather than AI training, where NVIDIA’s chips currently dominate.

Also, in a bid to seize the AI PC market opportunity, Apple’s new iPad Pro launched in early May has featured its in-house M4 chip. In an earlier report by Wccftech, Apple’s M4 chip adopts TSMC’s N3E process, aligning with Apple’s plans for a major performance upgrade for Mac.

In addition to Apple, with the flourishing of AI applications, TSMC has also reportedly beening working closely with the other two major AI giants, NVIDIA and AMD. It’s reported by the Economic Daily News that they have secured TSMC’s advanced packaging capacity for CoWoS and SoIC packaging through this year and the next, bolstering TSMC’s AI-related business orders.

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• [News] Apple M4 Incoming, Boosting TSMC’s 3nm Production
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(Photo credit: TSMC)

In addition to the aggressive overseas expansion plans recently, TSMC also demonstrates its ambition of increasing specialty capacity, targeting to be expanded by 50% by 2027, according to a report by AnandTech. A key driver of this demand will be TSMC’s forthcoming specialty node, N4e, a 4nm-class ultra-low-power production node.

Citing Kevin Zhang, TSMC’s Senior Vice President of the Business Development and Overseas Operations Office, the report revealed that TSMC plans to expand its specialty capacity by up to 1.5 times in the next four to five years. To accomplish this goal, it would not only convert existing capacity, but construct new fab space dedicated to specialty processes.

TSMC offers a range of specialty nodes catering to various applications such as power semiconductors, mixed analog I/O, and ultra-low-power applications (e.g., IoT), according to the report. Currently, the semiconductor giant’s most advanced specialty node is N6e, a variant derived from N7/N6 that accommodates operating voltages ranging from 0.4V to 0.9V. With N4e, TSMC aims to support voltages below 0.4V.

According to the materials TSMC provided in its latest earnings call, in the first quarter, HPC accounted for 46% of its total revenue, while IoT-related and automotive applications accounted for 6% of its total revenue, respectively. All the applications mentioned above are closely connected to specialty nodes.

TSMC’s overseas expansion plans are also closely related to its focus on specialty nodes. At the grand opening of JASM’s first Kumamoto plant in February, TSMC Chairman Mark Liu stated that JASM would use the latest green manufacturing practices to produce best-in-class specialty semiconductor technology.

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• [News] TSMC Reportedly Prepares Next-generation HBM4 Manufacturing, Utilizing 12nm and 5nm Process Nodes

(Photo credit: TSMC)

TSMC reportedly plans to utilize 12nm and 5nm process nodes in manufacturing the latest HBM4 memory, according to a report by AnandTech. Citing TSMC’s executives, the world’s largest dedicated semiconductor foundry would employ two fabrication processes, N12FFC+ and N5, to integrate HBM4e memory with next-generation AI and HPC processors.

During TSMC’s presentation at its European Technology Symposium 2024, which took place on May 14th, the company revealed new details about the base dies it will produce for HBM4 using advanced logic processes.

According to a senior director of design and technology platform citing by the report, TSMC is currently working with HBM memory partners, including Micron, Samsung and SK Hynix, on advanced nodes targeting HBM4.

Earlier in mid-April, SK Hynix announced that it has signed a memorandum of understanding with TSMC for collaboration to produce next-generation HBM and enhance logic and HBM integration through advanced packaging technology. The company plans to proceed with the development of HBM4, slated to be mass produced from 2026, through this initiative.

N12FFC+, believed to be more cost-effective, is expected to achieve HBM performance, while the N5 base die could offer more logic with significantly lower power.

In the symposium, TSMC stated that its 12FFC+ process is well-suited for HBM4 performance, enabling memory vendors to construct 12-Hi (48 GB) and 16-Hi (64 GB) stacks, with per-stack bandwidth exceeding 2 TB/second. It is also optimizing CoWoS-L and CoWoS-R for HBM4, which utilize over eight layers to support HBM4’s routing of over 2,000 interconnects with proper signal integrity.

These packaging solutions is said to provide interposers that can accommodate up to 8 times the reticle size, providing ample space for as many as 12 HBM4 memory stacks.

In addition, base dies produced with the N5 process will incorporate increased logic density, lower power consumption, and enhanced performance. However, the most significant advantage may lie in the extremely small interconnect pitches achievable with such advanced process technology, ranging from 6 to 9 microns. This capability will enable N5 base dies to be paired with direct bonding, facilitating the 3D stacking of HBM4 directly on top of logic chips. Direct bonding has the potential to significantly enhance memory performance, a crucial enhancement for AI and HPC chips constantly demanding higher memory bandwidth, according to the report.

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• [News] SK Hynix Partners with TSMC to Strengthen HBM Technological Leadership

(Photo credit: TSMC)

TrendForce’s latest findings revealed that as of 2024, Taiwan is expected to lead the global semiconductor foundry capacity in advanced manufacturing processes (including 16/14nm and more advanced technologies) with a 66% market share, followed by Korea (11%), US (10%), and China (9%). However, the semiconductor production capacities of advanced nodes in Taiwan and Korea are projected to decrease to 55% and 8%, respectively, by 2027.

It is worth noting that though semiconductor heavyweights including TSMC, SK Hynix and Samsung keep raising the amount of investments,  Taiwan and Korea, as the two countries holding the highest market share in advanced nodes, are expected to fall in their market shares.

On the other hand, in the US, where the government has been pushing incentives and subsidies more aggressively, its global capacity share in advanced manufacturing processes is expected to jump from 10% in 2024 to 22% in 2027.

Per the overall foundry capacity, Taiwan is expected to hold approximately 44% of global market share as of 2024, followed by China (28%), South Korea (12%), the US (6%), and Japan (2%). The overall trend is expected to be in line with advanced nodes. In contrast, the overall semiconductor production capacities of Taiwan and South Korea are projected to decrease to 40% and 10%, respectively, by 2027.

China, where foundries focus more on expanding mature process capacities and are backed by government subsidies, is projected to perform relatively strong in the overall global market share, growing from 28% in 2024 to 31% in 2027. Its market share of the matured process (including ≥28nm nodes) capacity is expected to rise from 33% in 2024 to 45% in 2027.

According to a report from THE CHOSUN Daily on May 10th, citing forecast from The Semiconductor Industry Association (SIA) and The Boston Consulting Group (BCG), in 2022, Taiwan and Korea held 69% and 31% shares of the production of the most advanced semiconductors below 10 nanometers, while their market share on the advanced nodes may fall to 47% and 9% in 2032, respectively.

The report as mentioned earlier stated that the dramatic decline in South Korea’s semiconductor production share is primarily attributed to key players like Samsung Electronics and SK Hynix, who currently dominate the global advanced semiconductor market alongside TSMC. However, instead of investing in South Korea, they have opted to establish their latest factories in the United States.

The US government announced earlier in April that it would provide up to USD 6.4 billion in subsidies to Samsung for expanding advanced chip production capacity at its Texas plant. In addition, SK Hynix plans to spend $3.87 billion building an advanced packaging plant and research center for artificial intelligence products in Indiana.

(Photo credit: Samsung)

Intel has secured its supply of the new High-NA EUV (high-numerical aperture extreme ultraviolet) lithography equipment from ASML, which the semiconductor heavyweight will allegedly use on its 18A (1.8nm) and 14A (1.4nm) nodes, according to reports from TheElec and Wccftech.

According to sources cited by TheElec, the Dutch fab equipment maker is manufacturing five units of the kit this year, which will all go to Intel, while Samsung and SK Hynix are expected to wait until the second half of 2025 to obtain the aforementioned equipment.

For companies aiming to produce 2-nanometer chips, High-NA EUV lithography equipment may be critical, with each unit priced at over 5 trillion Korean won (approximately US$ 370 million), indicating Intel’s total investment on ASML’s first batch of High-NA EUV kits may amount to US$ 2 billion, according to TheElec and Wccftech.

Intel has confirmed in mid-April that it has received and assembled the industry’s first High-NA EUV lithography system, which is expected to be able to print features up to 1.7x smaller than existing EUV tools. This will enable 2D feature scaling, resulting in up to 2.9x more density.

Compared to 0.33NA EUV, High NA EUV (or 0.55NA EUV) can deliver higher imaging contrast for similar features, which enables less light per exposure, thereby reducing the time required to print each layer and increasing wafer output.

Intel expects to use both 0.33NA EUV and 0.55NA EUV alongside other lithography processes in developing and manufacturing advanced chips, starting with product proof points on Intel 18A in 2025 and continuing into production of Intel 14A.

According to TSMC’s press release in late April, A16, TSMC’s next technology on its roadmap which will combine its Super Power Rail architecture with nanosheet transistors, is scheduled for production in 2026. However, citing Kevin Zhang, TSMC’s senior vice president of business development, Reuters reported that TSMC does not believe it needs to use ASML’s new High-NA EUV lithography tool machines to build the A16 chips.

(Photo credit: ASML)