In a bid to catch up with leading players like TSMC, the South Korean government is said to have approved a national-level initiative aimed at actively promoting the development of advanced chip packaging technologies, according to a report from South Korean media outlet TheElec.

Citing anonymous sources, the report on April 30th indicates that the feasibility of the aforementioned plan has passed the preliminary examination conducted by the Korea Institute of S&T Evaluation and Planning (KISTEP).

According to reports, the preliminary review targeted a national-level project with a value exceeding KRW 50 billion, with direct government sponsorship exceeding KRW 30 billion. Such projects rarely pass the review in one go, but the aforementioned chip packaging case is an exception.

Most of the reviewers at KISTEP have reportedly reached a consensus, recognizing the necessity of the project to catch up with leaders in advanced packaging like Taiwan’s TSMC, making South Korea a frontrunner.

As per TrendForce’s previous report, by 2027, Korea’s share in advanced process capacity is originally expected to reach 11.5%, with room for further growth.

However, the budget for the 7-year project has been reduced from the original KRW 500 billion to KRW 206.8 billion. After passing the preliminary feasibility review, the project is expected to be formally announced later this year (2024) and is scheduled to commence implementation next year.

Cited by the same report from TheElec, a source involved in the project stated that the budget cut was entirely expected, but the project’s single-pass approval is indeed noteworthy, indicating the government’s deep understanding of the importance of chip packaging.

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(Photo credit: TSMC)

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company’s 2024 North America Technology Symposium.

TSMC debuted the TSMC A16TM technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW™) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

“We are entering an AI-empowered world, where artificial intelligence not only runs in data centers, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”

New technologies introduced at the symposium include:

TSMC A16TM Technology: With TSMC’s industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap.

A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks.

Compared to TSMC’s N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15- 20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.

TSMC NanoFlexTM Innovation for Nanosheet Transistors: TSMC’s upcoming N2 technology will come with TSMC NanoFlex, the company’s next breakthrough in design-technology co optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.

N4C Technology: Bringing TSMC’s advanced techynology to a broader range of of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025.

N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.

CoWoS, SoIC, and System-on-Wafer (SoW): TSMC’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer. At the same time, our System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.

With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude.

TSMC’s first SoW offering, a logic only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

Silicon Photonics Integration: TSMC is developing Compact Universal Photonic Engine (COUPE ) technology to support the explosive growth in data transmission that comes with the AI boom. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

Automotive Advanced Packaging: After introducing the N3AE “Auto Early” process in 2023, TSMC continues to serve our automotive customers’ needs for greater computing power that meets the safety and quality demands of the highway by integrating advanced silicon with advanced packaging.

TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.

(Photo credit: TSMC)

According to TechNews, TSMC announced its latest updates on the evening of the 5th, stating that equipment within its Taiwan wafer fabs has largely recovered. The company’s full-year performance outlook, denominated in USD, is expected to remain consistent with the forecast provided during the January earnings call. Annual revenue is projected to grow in the low-to-mid twenties percentage range.

TSMC noted its robust experience and capabilities in earthquake response and disaster prevention, regularly conducting safety drills to ensure preparedness. Within just 10 hours of the earthquake on April 3rd, equipment recovery rates in the wafer fabs exceeded 70%, with newly constructed fabs like Fab 18 surpassing 80% recovery.

As of the 5th, except for certain production lines in areas with greater seismic impact requiring longer adjustment and calibration times to restore automated production, thanks to the concerted efforts of TSMC colleagues and supplier partners, equipment within Taiwan’s wafer fabs has largely recovered.

TSMC emphasized its comprehensive assessment of the earthquake’s impact and continues to maintain close communication with customers, providing timely updates on relevant impacts.

(Photo credit: TSMC)

Taiwan experienced a magnitude 7.2 earthquake on the 3rd, prompting round-the-clock repair efforts during the holiday by semiconductor fabs, aiming to restore equipment operations. According to reports from TechNews, the latest progress of various fabs and science parks across different locations is as follows.

TSMC

TSMC stated that the maximum intensity of the earthquake on the 3rd in science parks such as Hsinchu, Longtan, and Zhunan was magnitude 5, while in Central Taiwan and Southern Taiwan science parks, it was magnitude 4. The recovery rate of semiconductor fab equipment has exceeded 80%, with newly built fabs (such as Fab 18 responsible for producing 3 and 5 nanometers wafers) expected to fully recover by the evening of the 4th..

While some equipment in certain areas suffered damage, affecting production lines, major equipment including all EUV machines remained undamaged. In areas with higher seismic intensity, longer time is expected for adjusting and calibrating to restore automated production.

It is believed that this may refer to the advanced packaging stronghold in Longtan, where production process equipment needs reconfiguration due to earthquake evacuation, unstable or disrupted network signals requiring parameter reset, as well as seismic impacts on cleanroom spaces, damaged pipelines, and machinery relocation, all requiring extensive scheduling for repair.

UMC

A spokesperson for UMC indicated that the impact of the strong quake on 12-inch Fab in Southern Taiwan was relatively light, while 8-inch Fab in Hsinchu was more severely affected. The company’s machinery and pipelines remained undamaged, with only instances of machinery displacement, some quartz tube damage, sprinkler head damage, and partial office ceiling damage.

According to market sources cited in the same report, UMC is actively reallocating manpower to reposition machinery in 8-inch Fab, cleaning damaged wafers, and replacing quartz tubes, expecting a recovery time of two to three days, or even a week.

VIS

VIS stated that as of noon on the 4th, about 80% of affected machinery had returned to normal, and production operations would gradually resume. The company promptly informed affected customers upon the earthquake’s occurrence, maintaining close communication and providing detailed information individually.

Hsinchu Science Park Administration

Most major factories including semiconductor and panel manufacturing plants completed equipment recovery from the quake on the 3rd. Although there was some impact on production lines, effective measures were taken by factories such as seismic design for buildings and machinery, personnel evacuation, and preventive machinery shutdowns, resulting in minimal impact on factory operations.

Currently, factories are operating normally, with a few undergoing machine calibration for full recovery in the short term. Manufacturers’ machinery is gradually returning to operation, personnel have resumed their positions, and major wafer manufacturing plants have sufficient materials and are smoothly recovering operations.

Central Taiwan Science Park Administration

In parts of the Central Taiwan Science Park, which mainly focuses on optoelectronics, semiconductors, and precision machinery industries, manufacturers have gradually resumed operations after machinery shutdowns. Among them, over 90% of high-precision machinery in semiconductor fabs have resumed operation, with only some machines undergoing calibration, all expected to complete and operate normally by the end of the 4th.

Southern Taiwan Science Park Administration

As of noon on the 4th, major factories including TSMC, UMC, Innolux and Corning Taiwan in the area have all resumed normal operations. Continuous monitoring of aftershocks and manufacturer dynamics will be maintained, with necessary assistance provided as needed.

(Photo credit: TSMC)

On the morning of the 3rd April, a Richter scale 7.2 earthquake occurred, shaking the entire Taiwan. Semiconductor wafer foundries were also disrupted, and relevant manufacturers have carried out emergency evacuations according to SOP.

According to Money DJ, in response to the earthquake impact, TSMC is currently confirming detailed situations, while UMC has reported partial shutdowns of equipment and is making efforts to resume operations. As for PSMC, related evaluation is underway. The industry believes that the impact on the operations of related companies should be limited.

TSMC stated that, to ensure personnel safety, relevant preventive measures have been initiated according to internal company procedures. Some personnel in certain factory areas have been evacuated, and all personnel are currently safe and gradually returning to their workstations. Detailed situations are yet to be confirmed. Preliminary inspections of factory construction sites have shown normal conditions. For safety considerations, the company has decided to suspend work at construction sites across Taiwan today, and will resume after inspection.

The industry indicates that wafer fab buildings have quite high seismic resistance coefficients, capable of withstanding earthquakes of magnitude 7. However, typically occurring earthquakes of magnitude 3 to 4 may trigger machinery to activate defense mechanisms and auto shutdown. Whether normal operations will be resumed directly after restart, or if other damages occur, will require detailed inspections. Additionally, issues like wafers produced on the production line are partially damaged and ruptured quartz tubes and pipelines will require at least 1 to 2 days for further checking.

(Photo credit: CWA)