Nvidia CEO Jensen Huang announced on the 11th the company’s intention to deepen collaboration with high-tech companies in Vietnam, with a focus on fostering local expertise in AI and digital infrastructure development. Huang revealed plans to establish a chip center in Vietnam, as reported by Reuters.

According to documents released by the White House in September to enhance bilateral relations, Nvidia has invested USD 250 million in Vietnam. The company has strategically aligned with leading tech companies to implement AI technology in cloud computing, automotive, and healthcare industries.

This marks Huang’s first visit to Vietnam, where, during an event in Hanoi, he emphasized, “Vietnam is already our partner as we have millions of clients here.” He stated, “Vietnam and Nvidia will deepen our relations, with Viettel, FPT, Vingroup, VNG being the partners Nvidia looks to expand partnership with,” Huang said, adding Nvidia would support Vietnam’s artificial training and infrastructure.

Vietnam’s Minister of Planning and Investment, Chi Dung Nguyen, highlighted during the meeting on December 11th the country’s ongoing efforts to design mechanisms and incentives to attract investments in semiconductor and AI projects.

During his meeting with Vietnamese Prime Minister Pham Minh Chinh on the 10th, Huang shared the vision of establishing an R&D center, emphasizing that “the base will be for attracting talent from around the world to contribute to the development of Vietnam’s semiconductor ecosystem and digitalization.” Subsequently, on the 11th, Nguyen Chi Dung extended an invitation for Nvidia to consider establishing an R&D base in the country.

On the 11th, Nvidia engaged in discussions with the Vietnamese government and local tech companies regarding semiconductor cooperation agreements. According to insiders, Nvidia may potentially reach a technology transfer agreement with at least one Vietnamese company.

Given the strained trade relations between China and the U.S., Vietnam’s technology and manufacturing sectors are presented with a significant opportunity. The government actively seeks to enhance chip design capabilities and explore avenues for establishing a viable chip manufacturing industry.

Vietnam already serves as a pivotal IC packaging hub for global chip manufacturers. For instance, Intel boasts that it has world’s largest IC packaging and testing facility, is situated in Vietnam. Despite temporary delays in the expansion of its Vietnamese factory due to power supply and bureaucratic challenges, Intel affirmed in a Reuters interview, “Vietnam will continue to be a critical part of our global manufacturing operations as demand for semiconductors grows.”

Furthermore, several chipmakers have recently set up or expanded production facilities in Vietnam. Major OSAT provider Amkor commenced operations at its new USD 1.6 billion IC packaging plant in Yen Phong 2C Industrial Park, Bac Ninh Province, Vietnam, in October this year. A month earlier, Samsung’s OSAT partner, Hana Micron, announced the inauguration of its USD 600 million IC packaging plant in Bac Giang Province.

(Image: Nvidia)

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• [News] Amkor’s Vietnam Plant Meets High-End Semiconductor Demand as Advanced Packaging Thrives

Samsung, the Korean tech giant, has unveiled SAINT technology to counter TSMC’s advanced CoWoS packaging, aiming to benefit from the surging AI market. Market reports reveal that Samsung is strategically procuring a substantial amount of 2.5D packaging equipment, indicating a keen awareness of the soaring demand from AI chip companies like NVIDIA, reported by Korean media The Elec.

Samsung has acquired 16 sets of packaging equipment from the Japanese company Shinkawa. Currently, 7 sets have been received, with the possibility of additional orders based on future requirements. Samsung’s objective is to demonstrate its prowess in packaging and HBM technologies, seeking recognition and partnership with NVIDIA. As the limitations in NVIDIA’s current supply chain, especially due to insufficient CoWoS advanced packaging capacity in TSMC, Samsung emerges as a promising alternative for diverse supply chain.

On the other hand, NVIDIA’s ambitious goal of achieving USD 300 billion in AI sector revenue by 2027 requires a reliable supply chain, as per reported by TechNews. To this end, Samsung is poised to supply its next-gen GPU, Blackwell, featuring HBM3 and 2.5D packaging. This move aligns with NVIDIA’s strategy to diversify its supply chain away from existing providers like TSMC.

For Samsung, this collaboration presents a significant opportunity to enter the thriving AI market. Success in this venture could not only bolster the financial performance of Samsung’s memory and advanced packaging divisions but also open doors to orders from players like AMD and Tesla. However, the key lies in how effectively Samsung meets the formidable market demand, particularly in semiconductor production, advanced packaging, and memory technology.

(Image: Samsung)

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• [News] TSMC’s CoWoS Demand Surges from NVIDIA, Apple, AMD, Broadcom, Marvell, Monthly Capacity Up 120% in 2024

The AI landscape witnesses a robust surge with the consecutive launches of AMD’s “Instinct MI300” series AI chips and NVIDIA’s upcoming “B100” GPU structure. This wave of innovation propels a flourishing demand for AI-related Outsourced Semiconductor Assembly And Test Services (OSAT), surpassing initial estimates by over 10%. OSAT companies like ASE Holdings, King Yuan Electronics (KYEC), and Sigurd are poised to experience a notable uptick in revenue, as reported by UDN News.

According to reports, AMD is launching the “Instinct MI300” series AI chips this week, and NVIDIA plans to unveil the next-gen “B100” GPU next year. This successive release of new AI products by the two giants is boosting momentum in related OSATs collaboration.

NVIDIA is gearing up for the 2024 launch of its next-gen Blackwell architecture B100 GPU, saying AI performance exceeding twice that of the H200 GPU under the Hopper architecture, signifying a substantial leap in computational prowess.

Positive Outlook in 2024 for OSATs Amid AI Chip Development

Industry source indicates that due to the AI extensive computation requirements, advanced packaging is gradually becoming mainstream. This involves stacking chips and packaging them on a substrate. Depending on the arrangement, it is divided into 2.5D and 3D packaging. The advantage of this packaging technology is the ability to reduce chip space while also reducing power consumption and costs.

It is said the surge in AI chip orders from AMD and NVIDIA has led to a bottleneck in TSMC CoWoS advanced packaging capacity. This unexpected demand has exceeded projections for related OSATs, including ASE Holdings, KYEC, and Sigurd.

In the case of ASE Holdings, its subsidiary Siliconware Precision Industries (SPIL) possesses the advanced packaging capacity essential for generative AI chips. Joseph Tung, CFO of ASE Holdings, notes that while AI currently in its early-stage and is set to drive explosive growth. As AI integrates into existing and new applications, the demand for advanced packaging is expected to fuel the industry’s entry into the next super growth cycle.

For KYEC, a significant expansion in AI chip testing capacity since Q2 this year positions the company to benefit from the surge in demand.

Sigurd’s COO Tsan-Lien Yeh addresses that, with the release of AI phones, recognizing the doubled testing time for phone chips, which now carry APU/NPU for AI computing compared to general 5G chips. Sigurd has upgraded its equipment to align with future customer needs.

(Image: ASE VIPack’s video)

According to TechNews’ report, Apple, NVIDIA, AMD, Qualcomm, and MediaTek all utilize TSMC’s semiconductor processes for manufacturing their latest chips, with some potentially employing Samsung’s foundry, though typically not for flagship products.

With Samsung’s improved yield rates in recent months, the company is eager to secure a portion of the orders, particularly for the 3-nanometer GAA (Gate-All-Around) process.

Earlier market reports suggested that Qualcomm’s Snapdragon 8 Gen 4 might adopt a dual-foundry strategy, simultaneously utilizing TSMC’s N3E process technology and Samsung’s SF3E process technology.

However, both Qualcomm and MediaTek currently plan to employ TSMC’s second-generation 3-nanometer process technology (N3E) for manufacturing chips like the Snapdragon 8 Gen 4 and Dimensity 4, without pursuing a dual-foundry strategy at this time.

As of the end of June 2022, Samsung announced the commencement of production for 3-nanometer process chips at its Hwaseong Industrial Complex in South Korea. These chips incorporate a new GAA transistor architecture technology, rumored to be more energy-efficient compared to TSMC’s 3-nanometer FinFET technology. Despite this, in the realm of 3nm, Samsung has yet to secure substantial orders from major clients.

Interestingly, the company has seen more success in the 4nm domain. It is reported that Samsung has gradually addressed yield and various issues in the 4-nanometer process technology domain. The third generation of 4-nanometer process technology has seen improvements in performance, reduced power consumption, increased density, and achieved yields close to TSMC’s level. Market sources indicate that Samsung has gained recognition from companies like AMD and Tesla, securing new orders.

Currently, TSMC’s 3-nanometer process technology production capacity is ramping up, with an expected monthly capacity of 100,000 wafers by the end of 2024. The revenue contribution is projected to increase from the current 5% to 10%.

Meanwhile, Samsung plans to introduce the second generation of its 3-nanometer process technology, named SF3 (3GAP), in 2024. Building upon the existing SF3E, it aims for further optimization, and Samsung’s in-house Exynos 2500 is expected to be one of the first high-performance chips to adopt this new process technology.

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• [News] A battle on 4nm: AMD Teams Up with Samsung, while Google Weighs Supplier Split

Equipment is playing an indispensable role during the wafer manufacturing process. In response to market needs, the global EUV lithography supplier, ASML, has recently taken significant steps.

ASML’s Bold Move: Annual Investment of EUR 100 Million in Berlin Plant

As reported by the German media “Handelsblatt,” the Netherlands-based company ASML plans to invest EUR 100 million (USD 109 million) in 2023, with a similar annual investment in the subsequent years. This investment aims to enhance the production and development capabilities of ASML’s manufacturing plant located in Berlin, Germany.

Reports indicate that ASML’s Berlin plant primarily produced core components of EUV equipment, including wafer clamps, wafer tables, reticle chucks and mirror blocks. ASML acquired this facility, known as “Berliner Glas,” in 2020.

Foundries Actively Pursue EUV equipment

The EUV equipment plays a crucial role in manufacturing, utilizing specific wavelength light for radiation to precisely imprint images on wafers. Currently, the EUV equipment market is highly concentrated, with only a few global companies mastering this technology. Among them, Dutch company ASML stands out as the world’s largest and most advanced EUV company. Additionally, companies like Nikon, Canon, and Shanghai Micro Electronics Equipment (SMEE) are strategically positioning themselves in the EUV sector.

EUV technology, used for exposing semiconductor process, is indispensable due to its high cost, complex processes, and limited supply. ASML is the sole global supplier of EUV. For advanced processes below 7nm, EUV serves as an essential device. Developed over more than 20 years, EUV technology has become the cornerstone of advanced processes, enabling the continuation of Moore’s Law for at least another decade.

As a crucial EUV equipment supplier, ASML is working on a new generation of NA-EUV equipment, where “NA” represents numerical aperture. A higher NA value means a higher achievable resolution, allowing for more transistors on the chip. It is expected that by the year-end, ASML will unveil the world’s first high-NA EUV and deliver it to Intel.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

TSMC’s 2nm process will continue to leverage EUV technology. In a previous announcement in September, TSMC disclosed the acquisition of Intel’s subsidiary IMS for up to US 432.8 million, focusing on the research and production of electron beam lithography machines. Industry experts believe that TSMC’s move ensures the technical development of critical equipment and meets the supply demand for the commercialization of 2nm.

Following 2nm chips. Samsung plans to achieve mass production of 2nm processes in the mobile field by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively. According to the report in September, Samsung is gearing up to secure the yield of the next-generation EUV equipment, High-NA, with the prototype expected to launch later this year and official supply next year.

After announcing its return to the foundry business, Intel revealed in October that it has commenced mass production of Intel 4 process nodes using EUV technology. Currently, both Intel 7 and Intel 4 have achieved mass production, and Intel 3 is progressing according to plan, with the goal of completion by the end of 2023.

(Image: ASML)