As semiconductor manufacturing processes evolve more gradually, 3D packaging emerges as an effective means of prolonging Moore’s Law and enhancing the computational prowess of ICs. Within the realm of 3D stacking technology, the Interuniversity Microelectronics Centre (imec) based in Belgium categorizes 3D integration technologies into four distinct types, each determined by different partitioning locations within a chip: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC. Based on our previous discussion of 3D-SIP and 3D-SIC stacking, this article places a spotlight on the other two technologies: 3D-SOC and 3D-IC.

Related Article: Differences Between 3D-SIP and 3D-SIC: Why Are TSMC, Intel, and Samsung All Actively Involved?

3D-SOC

A System on Chip (SOC) involves the redesign of several different chips, all fabricated using the same manufacturing process, and integrates them onto a single chip. 3D-SOC takes this concept to new heights by stacking multiple SOC chips vertically. The image below illustrates the transformation of a 2D System on Chip (2D-SOC), where circuits are redivided into blocks, and then stacked to form a 3D System on Chip (3D-SOC).

Source: imec

imec’s research team previously published a paper on IEEE, outlining the advantages of 3D-SOC and backside interconnects. This technology aims to achieve the integration of diverse chips in a heterogeneous system. By intelligently partitioning circuits, it significantly reduces power consumption and boosts computational performance. In comparison to the trending chiplet technology, 3D-SOC holds a competitive edge.

Eric Beyne, IMEC’s Vice President of Research and Project Director for 3D System Integration, pointed out, “Chiplets involve separately designed and processed chiplet dies. A well-known example are high-bandwidth memories (HBMs) – stacks of dynamic random access memory (DRAM) chips. This memory stack connects to a processor chip through interface buses, which limit their use to latency-tolerant applications. As such, the chiplet concept will never allow for fast access between logic and first and intermediate level cache memories.”

However, it’s essential to acknowledge that 3D-SOC technology comes with apparent drawbacks, primarily higher research and development costs and a longer development timeline compared to 3D-SIP technology. Nevertheless, as applications like AIGC, AR/VR, 8K, and others continue to drive the need for high-speed computing, chips are relentlessly progressing towards higher efficiency, lower power consumption, and smaller size. In this context, 3D-SOC technology will maintain its place in advanced packaging.

Backside Power Delivery Network (BSPDN)

The technology of Backside Power Delivery Network (BSPDN) represents a pivotal development in semiconductor manufacturing, offering several advantages, including more flexible circuit design, shorter metal wire lengths, and higher chip utilization. After transforming a 2D System on Chip (2D-SOC) into a 3D-SOC through layered stacking, the original back sides of the chips become the outer sides of the 3D-SOC. At this stage, the “freed-up” backside of the chips can be utilized for signal routing or as power lines for transistors, in contrast to traditional processes where wiring and power lines are designed on the front side of the wafer.

In the past, backside chips were merely used as carriers, but BSPDN technology allows for more space to be used for logic wafer design. According to simulation results, the transmission efficiency of backside PDN is seven times higher than traditional front-side PDN. Intel has also announced the introduction of this technology in the 20Å and 18Å processes.

To achieve BSPDN, a dedicated wafer thinning process (reducing it to a few hundred nanometers) is required, along with nanoscale through-silicon vias (nTSV) to connect backside power to the front-side logic chip.

Another key technology for BSPDN is the Buried Power Rail (BPR), a miniaturization technique that embeds wires beneath the transistors, with some inside the silicon substrate and others in shallow trench isolation oxide layers. BPR replaces power lines and ground lines under standard cells in traditional processes and further reduces the width of standard cells, mitigating IR voltage drop issues.

The diagram below illustrates BSPDN, where backside PDN’s metal wiring is connected to Buried Power Rails (BPR), and the backside of the chip (BS) is connected to the front side of the logic chip (FS).

Source: imec

3D-IC

The final category, 3D-IC, employs new 3D sequential technology (S3D) or Monolithic technology to vertically stack n-type and p-type transistors, forming a Complementary Field-Effect Transistor (CFET). This technology enables two transistors to be stacked and integrated into the size of a single transistor. This not only significantly increases transistor density but also simplifies the layout of CMOS logic circuits, enhancing design efficiency. As seen in the diagram below, n-type and p-type transistors are integrated vertically to form a CFET.

Source: imec

Nevertheless, the key challenge lies in how to vertically integrate each minuscule transistor and address heat dissipation issues under high-speed computing. Major manufacturers are still in the development phase, but the technology’s biggest advantage lies in achieving the highest component density and the smallest node width, even without nodes. With the continuous increase in demand for high-speed computing, 3D-IC technology is set to become a focal point in the industry’s development.

3D Stacking Leading the Global Semiconductor Advancement

imec has outlined a roadmap for 3D stacking, aiming to reduce pitch spacings and increase point density within unit areas. However, imec also emphasizes that the development of 3D packaging technologies does not follow a linear timeline, as depicted in the figure above, as there is no single packaging technology that can cater to all requirements.

With the rapid development of applications such as AIGC, AR/VR, 8K, 5G, and others, a significant demand for computing power is expected to persist. To overcome the bottlenecks in semiconductor process technology, countries worldwide are fully engaged in advanced packaging research, and 3D stacking undoubtedly takes the center stage as the elixir for Moore’s Law continuation.

Explore More

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• Intel and Samsung Join TSMC in Fierce Advanced Packaging Race
• Continuing Moore’s Law: Advanced Packaging Enters the 3D Stacked CPU/GPU Era
• Understanding Chiplets, SoC, and SiP: Why TSMC, Intel, Samsung Invest?

(Image: Samsung)

In recent developments, Samsung Foundry, a subsidiary of Samsung Electronics, has disclosed that it has initiated discussions with major chip clients, gearing up to provide services utilizing 1.4nm and 2nm processes.

It’s been said that Samsung being ahead in the production of 3nm GAA (gate-all-around) process, yet not as favored by major clients as TSMC. In response to the comment, Ki-tae Jeong, the CTO of Samsung Foundry, had share his insights at Semiconductor Expo 2023 in South Korea.

According to the Chosun Ilboon’s report, Jeong pointed out that in the semiconductor foundry industry, it typically takes approximately 3 years for major clients to make their final purchasing decisions. Samsung is actively engaging with prominent clients, and results may become evident in the coming years. Also, the company is currently discussing future processes such as 2nm and 1.4nm with major clients.

How are advanced semiconductor processes progressing?

Compared to mature processes, advanced processes are better suited for applications that demand high performance and low power consumption. With emerging technologies like AI and high-performance computing driving the industry, the demand for advanced processes continues to rise. Leading semiconductor companies are committed to developing new technologies, with chip advanced processes evolving from 5nm to 4nm and now down to 3nm, while looking ahead to the possibility of reaching 2nm and 1.4nm.

Current progress from major players:

Samsung
Samsung has already commenced mass production of its second-generation 3nm chips and aims to introduce the 2nm process by the end of 2025, with the 1.4nm process expected by the end of 2027.

TSMC
TSMC is planning to start production for N3P in the latter half of 2024, with N3X and the 2nm process set to enter mass production in 2025. TSMC will introduce Gate-all-around FETs (GAAFET) transistors for the first time at the 2nm process node, offering a 15% speed increase at the same power consumption and up to a 30% reduction in power consumption at the same speed, all while increasing chip density by more than 15%.

Intel
Intel is diligently pursuing its “Four Years, Five Nodes” plan. Presently, Intel 7 and Intel 4 are in mass production, and the Intel 3 process is expected to enter the readiness for production stage in the latter half of this year. Subsequently, Intel 20A and 18A processes are planned to enter the readiness for production stage in the first and second halves of 2024, respectively.

Moreover, industry experts believe that in the near term, Intel will focus on the Intel 3 process as its flagship offering in the advanced process semiconductor foundry sector to compete with TSMC, Samsung, and other players.

ASE Holdings conducted an earning conference on October 26th to unveil its Q3 financial results and offer insights into future business prospects. All eyes are on ASE’s progress in CoWoS advanced packaging. Joseph Tung, the Chief Financial Officer (CFO) of ASE, expressed confidence in AI and ongoing investments in advanced packaging, expecting a twofold increase in revenue share for advanced packaging in the coming year.

The market’s attention is keenly focused on wafer bank (a storage system used in semiconductor manufacturing to keep semiconductor wafers on hand for production, helping to streamline the manufacturing process) levels and inventory management. Tung mentioned that wafer bank levels are consistently declining and will further reduce Q4. With consumer electronics and computer clients gearing up to launch new products, inventory levels are expected to be maintained at a certain level. Overall, inventory reduction is nearing completion.

Tung emphasized that the real challenge lies not in inventory reduction but in the timing of the recovery in consumer demands and the impact of inflation. ASE remains cautious in its outlook for the upcoming year.

As for AI-related developments, Tung is optimistic about the expansion of CoWoS advanced packaging capacity through TSMC. ASE is also set to boost its production capacity for advanced packaging to cater to urgent customer demands. Next year, it is expected that revenue in advanced packaging will double. Tung emphasized that the AI era has already arrived and expects AI to extend to more terminal devices over the next few years. ASE has also invested in the development of Co-Packaged Optics (CPO) technology, ready to meet customer demands when the market is prepared.

To seize opportunities in advanced packaging, ASE previously introduced an Integrated Design Ecosystem (IDE) to optimize collaborative design tools through a platform, systematically enhancing advanced packaging architecture. This initiative has the potential to reduce design cycles by approximately 50%.

Tung pointed out that there are signs of a recovery in PC-related chip testing and packaging, and this year’s performance in automotive chip testing and packaging is expected to outperform other segments.

Looking ahead to future market conditions, Tung believes that the global semiconductor industry’s environment in the coming year will be more favorable than the current year.

(Image: ASE)

On October 17, 2023, the U.S. government unveiled an updated set of regulations for semiconductor exports, introducing stricter standards for advanced AI chips. Additionally, these regulations expand control over the export of exposure equipment and include Chinese GPU design startups on an Entity List.

TrendForce’s Insights: 

1. New regulations cover chips, manufacturing equipment, and related companies, signaling an effort to restrain China’s AI development.

In this latest set of regulations, the U.S. has relaxed the I/O bandwidth restrictions for AI chips and introduced three additional conditions beyond a total processing performance (TPP) of ≥ 4800 TOPS:

(1) Total processing performance ≥ 1600 TOPS and performance density (PD) ≥ 5.92

(2) Total processing performance ≥ 2400 TOPS but < 4800 TOPS and performance density ≥ 1.6 but < 5.92

(3) Total processing performance ≥ 1600 TOPS and performance density ≥ 3.2 but < 5.92

As a result of these new conditions, NVIDIA’s A800, H800 GPU, and the recent launched L40S GPU for the Chinese market are now included in the list of controlled exports, similar to the A100 and H100 GPUs that were added in September 2022.

Concerning manufacturing equipment, the control threshold for exposure equipment has shifted from single-machine (specified substrate) coverage precision of ≤ 1.5nm to > 1.5nm but ≤ 2.4nm. This change directly led to the inclusion of ASML’s 1980Di DUV lithography machines.

On the corporate front, Chinese domestic GPU design startups such as Birentech, Moore Threads, and high-speed DSP design company Superfusion Semiconductor, along with their related entities, have been placed on the Entity List by the U.S. Department of Commerce.

In summary, these new regulations encompass chips, manufacturing equipment, and related companies. The U.S. is not only controlling the current mainstream AI product lines and applications of DUV lithography machines for 28-7nm processes but is also making a clear effort to interfere Chinese domestic manufacturers’ development of AI computation chips, indicating a strong determination to restrict China’s growth in the AI sector.

2. Priority for Chinese Enterprises: Securing AI Computing Resources through Cloud Service Providers

In light of the impact of the new U.S. semiconductor control regulations, Chinese domestic companies will be limited to AI chip performance not exceeding that of NVIDIA L40 GPU. As leading companies like NVIDIA, AMD, Intel, and others continuously boost the performance of their AI chips, the gap between the AI computing resources established by Chinese companies and their international counterparts will continue to widen.

Looking at it from an angle of independent research and development, with the inclusion of 1980Di and more advanced DUV lithography machines in the control list and the U.S. Department of Commerce placing Chinese IC design companies on the Entity List, short-term mass production of high-performance server AI chips in China seems unlikely.

Faced with challenges in both outsourcing and in-house production, the primary path for Chinese domestic companies to develop AI technology and applications is to obtain high-performance AI computing resources from international cloud service providers (CSP). It is worth noting that the U.S. government is also exploring limitations on Chinese firms attempting to evade semiconductor control policies through CSP. For Chinese companies, establishing robust customer relationships and building extensive AI computing resources are pressing priorities before related policies are enacted.
(Image: Pixabay)

According to a report by Bloomberg, Yoshihiro Seki, Secretary-General of the ruling Liberal Democratic Party and a member of the Japanese parliament, has announced that the government is planning to allocate an additional ¥900 billion for the construction of TSMC’s Fab 2 in Kumamoto, Japan. Furthermore, an extra ¥590 billion in subsidies will be provided to support the construction of a wafer fab by the Japanese semiconductor startup Rapidus.

Seki emphasized that subsidies usually cover about one-third of the total investment. With measures like training Japanese engineers and collaborative R&D with local companies, this subsidy could increase to potentially cover up to half of the investment. He also noted that the specific amount remains subject to change as the additional budget has not been finalized yet.

The Japanese government initiated the “Strategy for Semiconductors and the Digital Industry” in 2021 to address economic risks and prepare for the wave of digitalization. At that time, they already provided ¥476 billion in subsidies for TSMC’s Kumamoto 1st Fab. The current subsidy marks an expansion of these efforts.

The local government Kumamoto is eagerly anticipating TSMC’s presence. Ikuo Kabashima, the Governor of Kumamoto Prefecture, recently proposed “New Airport Concept Next Stage” that envisions using the airport as a hub for semiconductor imports and exports over the next decade. This plan aims to stimulate the clustering of semiconductor-related industries and contribute to regional development centered around Kumamoto.

Moreover, the Japanese government has pledged to provide ¥330 billion in funding to enable Rapidus to construct a 2nm wafer fab in Hokkaido. These substantial subsidies underscore the Japanese government’s commitment to these semiconductor projects.

In response to the Japanese government’s additional subsidies, Tetsuro Higashi, Chairman of Rapidus, stated in an interview with Jiji Press on the 24th that apart from the new factory being built in Chitose, Hokkaido, “We also plan to construct second and third factories, and they will also be situated in Chitose, Hokkaido.” Rapidus’s 2nm chip R&D/production facility, Chitose Fab IIM-1, located in the Chitose Meimeimei World industrial park in Chitose, Hokkaido, commenced construction in September. The trial production line is expected to start in April 2025, with mass production slated to begin in 2027.