According to a report by Taiwan’s Commercial Times, JPMorgan’s latest analysis reveals that AI demand will remain robust in the second half of the year. Encouragingly, TSMC’s CoWoS capacity expansion progress is set to exceed expectations, with production capacity projected to reach 28,000 to 30,000 wafers per month by the end of next year.

The trajectory of CoWoS capacity expansion is anticipated to accelerate notably in the latter half of 2024. This trend isn’t limited to TSMC alone; other players outside the TSMC are also actively expanding their CoWoS-like production capabilities to meet the soaring demands of AI applications.

Gokul Hariharan, Head of Research for JPMorgan Taiwan, highlighted that industry surveys indicate strong and unabated AI demand in the latter half of the year. Shortages amounting to 20% to 30% are observed with CoWoS capacity being a key bottleneck and high-bandwidth memory (HBM) also facing supply shortages.

JPMorgan’s estimates indicate that Nvidia will account for 60% of the overall CoWoS demand in 2023. TSMC is expected to produce around 1.8 to 1.9 million sets of H100 chips, followed by significant demand from Broadcom, AWS’ Inferentia chips, and Xilinx. Looking ahead to 2024, TSMC’s continuous capacity expansion is projected to supply Nvidia with approximately 4.1 to 4.2 million sets of H100 chips.

Apart from TSMC’s proactive expansion of CoWoS capacity, Hariharan predicts that other assembly and test facilities are also accelerating their expansion of CoWoS-like capacities.

For instance, UMC is preparing to have a monthly capacity of 5,000 to 6,000 wafers for the interposer layer by the latter half of 2024. Amkor is expected to provide a certain capacity for chip-on-wafer stacking technology, and ASE Group will offer chip-on-substrate bonding capacity. However, these additional capacities might face challenges in ramping up production for the latest products like H100, potentially focusing more on older-generation products like A100 and A800.

(Photo credit: TSMC)

As semiconductor process technology nears known physical limits, the spotlight among major industry players is shifting towards the development of advanced packaging. Concurrently, the rise of applications like artificial intelligence and AIGC has propelled the concept of advanced packaging into a new technological wave. In the midst of the semiconductor industry’s global competition, securing more orders has become a core objective for major players.

A Competitive Landscape in Advanced Packaging

The competition in advanced packaging technology is intensifying, with companies pouring substantial investments into the field, resulting in a landscape of vigorous competition. Various packaging technologies have emerged, with notable offerings from industry giants such as TSMC, Intel, and Samsung.

TSMC introduced 3DFabric, an integration of its TSMC-SoIC front-end technology with CoWoS and InFO back-end technologies, providing maximum flexibility for diverse innovative product designs.

Intel, on the other hand, features its 2.5D EMIB and 3D Foveros packaging technologies. EMIB is applied in the connection of logic chips and high-bandwidth memory, as seen in the Intel Xeon Max series and Intel Data Center GPU Max series.

Foveros allows top dies to overcome size limitations and accommodate more top and base dies, connected through copper pillars to reduce potential interference from through-silicon vias (TSVs).

Samsung also exhibits strong competitiveness in advanced packaging, with its 2.5D I-Cube4 and H-Cube, along with 3D X-Cube packaging technologies, achieving breakthroughs in multi-chip interconnects and integration.

Samsung’s I-Cube4, for example, integrates four HBM stack dies and one core compute IC on the silicon interposer layer, while H-Cube enhances packaging area through the stacking of HDI PCBs to accommodate designs with six or more HBM stack dies.

Advantages of the Three Giants

In recent years, the three semiconductor giants have directed substantial capital expenditure towards advanced packaging. Their diverse technological developments and marketing strategies are poised to ignite a global battle in the semiconductor advanced packaging industry.

TSMC holds the advantage with its dominant wafer process technology and an end-to-end comprehensive service approach. Coupled with Taiwan’s robust semiconductor ecosystem, TSMC leads the way in the advanced packaging domain.

Intel, while slightly trailing TSMC in advanced process technology, matches it in advanced packaging capabilities. Emphasizing flexible foundry services, Intel allows clients to mix and match its wafer manufacturing and packaging offerings. With manufacturing facilities scattered worldwide, Intel leverages geographic advantages, particularly in Western countries, to expand capacity and services, leading to anticipated gains in the future.

Samsung, like TSMC, offers end-to-end services, but its packaging technology lags behind TSMC’s. It secures a share in constrained supply situations. Notably, Samsung, in June 2022, was ahead of TSMC in unveiling the innovative GAA 3nm process, and is poised to combine it with 3D packaging technology, potentially marking a pivotal point in the next semiconductor generation.

With semiconductor technology’s continuous evolution and surging market demand, the competition among the three giants in advanced packaging will remain fierce. While wafer fabs currently prioritize processes, the next three to five years are expected to witness a gradual shift towards advanced packaging. Different packaging technologies and marketing strategies will ultimately determine companies’ positions and influence in the market.

(Photo credit: TSMC)

Read more:

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• ASE, Amkor, UMC and Samsung Getting a Slice of the CoWoS Market from AI Chips, Challenging TSMC

According to a report by Taiwan Economic Daily, industry sources have revealed that due to sluggish terminal demand and market competition, TSMC and Vanguard have recently been progressively lowering their prices for 8-inch wafer foundry services, with reductions as high as 30%.

While 8-inch wafer foundry services do not constitute a major portion of TSMC’s revenue, the company has historically maintained a relatively steadfast pricing strategy, refraining from frequent price hikes or reductions. The current reduction of up to 30% has raised significant attention.

The report states that the semiconductor industry is experiencing a downturn in prosperity, resulting in decreased capacity utilization at wafer foundries. Within this context, demand for 8-inch wafers is weaker compared to 12-inch wafers, leading some manufacturers to see their 8-inch wafer utilization rates drop to around 60%.

Regarding the price reduction, analysts at Nomura Securities suggest that this move is primarily aimed at countering Texas Instruments (TI), a global leader in analog ICs, which has significantly lowered prices for products such as power management ICs, triggering a worldwide semiconductor price war that has impacted related industries. In response, IC design companies are hoping for price reductions from foundries such as TSMC and to lower costs and compete against TI.

IC design firms have indicated that they have not received any official notification of price reductions for 8-inch wafer foundry services. They emphasized that TSMC has never implemented such a substantial reduction of up to 30% since its establishment, raising doubts about the authenticity of the news. TSMC has declined to comment on pricing matters.

(Photo credit: TSMC)

TSMC previously announced in November 2021 that it plans to establish two wafer fabrication plants for the 7nm and 28nm processes in Kaohsiung, a southern city of Taiwan. Construction was set to begin in 2022, with official production expected to commence in 2024. However, following the announcement, there have been changes in the progress of the Kaohsiung plant development.

Firstly, there were reports of adjustments to the 7nm plant by the end of 2022, in response to weakened demand in the smartphone and PC markets. Subsequently, there were also reports of changes to the 28nm plant’s plans.

It wasn’t until TSMC’s Q1 2023 earnings conference that they officially announced the adjustment of the Kaohsiung 28nm plant’s construction plans, focusing on capacity enhancement for more advanced process technologies.

At the time, TSMC didn’t specify the exact advanced process that would be introduced, only emphasizing that the construction of the wafer fab would proceed as planned. This triggered market speculation that TSMC was likely to adopt the advanced 2nm process technology at the Kaohsiung plant, in response to the rapidly growing demand in the artificial intelligence market.

This week, TSMC confirmed that the Kaohsiung plant will adopt the 2nm process technology. TSMC stated that the construction of the wafer fab in Kaohsiung will proceed as usual, but the previous expansion plans will be adjusted to accommodate the production of the 2nm advanced process technology, in response to strong market demand for advanced processes.

As for the specific details and contents of the plant development, they have not been further disclosed at this stage. According to TSMC’s plans, mass production of the 2nm process is expected to begin in 2025, with production bases including the previously announced Hsinchu and Taichung facilities, as well as the newly announced Kaohsiung facility.

(Photo credit: TSMC)

Leading semiconductor companies TSMC, Robert Bosch GmbH, Infineon, and NXP Semiconductors have jointly to invest in the European Semiconductor Manufacturing Company (ESMC) GmbH, situated in Dresden, Germany. This strategic move aims to bolster the region’s semiconductor manufacturing capabilities, particularly catering to the burgeoning automotive and industrial sectors. The establishment of ESMC marks a significant stride towards the realization of a 300mm fabrication facility, pending the final decision on public funding, as part of the European Chips Act framework.

The planned fab is expected to have a monthly production capacity of 40,000 300mm (12-inch) wafers on TSMC’s 28/22 nanometer planar CMOS and 16/12 nanometer FinFET process technology, further strengthening Europe’s semiconductor manufacturing ecosystem with advanced FinFET transistor technology and creating about 2,000 direct high-tech professional jobs. ESMC aims to begin construction of the fab in the second half of 2024 with production targeted to begin by the end of 2027.

The prospective joint venture will see TSMC holding a substantial 70% ownership stake, while Bosch, Infineon, and NXP will each possess a 10% equity share, contingent upon regulatory approvals and meeting specific conditions. Total investments exceeding 10 billion euros are anticipated. Operational oversight of the fabrication facility will reside under TSMC’s purview.

However, industry analysts at TrendForce have highlighted potential challenges that lie ahead for TSMC’s groundbreaking endeavor. One such challenge pertains to the looming labor shortage issue in TSMC’s US fabrication facility, which is projected to reverberate globally. Moreover, navigating the intricacies of implementing subsidy policies in accordance with the European chip legislation and anticipated administrative procedures is expected to introduce a layer of complexity to the venture.

(Photo credit: TSMC)