Driven by emerging technologies like AI and high-performance computing, the semiconductor foundry industry increasingly emphasizes the importance of advanced manufacturing processes. Recently, the industry has seen significant developments. Intel announced that it has commenced large-scale production of its Intel 4 process node, while TSMC and Samsung are equally committed to advancing their advanced process technologies.

Intel’s Mass Production of Intel 4 Process Node

On October 15th, Intel China’s official public account revealed that Intel has initiated large-scale production of the Intel 4 process node using Extreme Ultraviolet Lithography (EUV) technology. According to Intel, they are making significant progress with their “Four Years, Five Nodes” plan. This plan aims to produce next-generation products that meet the computational demands driven by AI’s role in the “Siliconomy.”

Being the first process node produced by Intel using EUV lithography technology, Intel 4 offers substantial improvements in performance, efficiency, and transistor density compared to its predecessors. Intel 4 was unveiled at the Intel Innovation 2023 held in September this year.

In comparison to Intel 7, Intel 4 achieves a 2x reduction in area, providing high-performance computing (HPC) logic libraries and incorporating various innovative features.

In detail, Intel 4 simplifies the EUV lithography process, optimizing it for high-performance computing applications, supporting both low voltage (<0.65V) and high voltage (>1.1V) operations. Compared to Intel 7, Intel 4 boasts more than a 20% improvement in iso-power performance, and high-density Metal-Insulator-Metal (MIM) capacitors deliver outstanding power supply performance.

Intel 7 and Intel 4 are currently in large-scale production. Intel 3 is on track to meet its planned target by the end of 2023.

Intel’s Intel 20A and Intel 18A, which use Ribbon FET all-around gate transistors and PowerVia backside power delivery technology, are also progressing well, with a target of 2024. Intel will soon introduce the Intel 18A process design kit (PDK) for Intel Foundry Services (IFS) customers.

With the adoption of Intel 4 process nodes, the Intel Core i9 Ultra processor, codenamed “Meteor Lake,” will be released on December 14th this year, ushering in the AIPC era.

On Intel 3 process nodes, the energy-efficient E-core Sierra Forest processor will be launched in the first half of 2024, and the high-performance P-core Granite Rapids processor will follow closely.

Samsung’s 2nm Process Detailed Production Plan

Samsung has already commenced production of its second-generation 3nm chips and plans to continue focusing on 2nm chips.

On June 28th, Samsung Electronics unveiled its latest foundry technology innovations and business strategies at the 7th Samsung Foundry Forum (SFF) in 2023.

In the era of artificial intelligence, Samsung’s foundry program, based on advanced GAA process technology, offers robust support for customers in AI applications. To this end, Samsung has disclosed a detailed production plan and performance levels for its 2nm process. The plan is to achieve mass production for mobile applications by 2025 and respectively expand to HPC and automotive electronics in 2026 and 2027.

Samsung reports that the 2nm process (SF2) improves performance by 12% compared to the 3nm process (SF3), increases efficiency by 25%, and reduces the area by 5%.

Furthermore, reports indicated that Samsung is ensuring the production capacity for products using the next-generation EUV lithography machine, High-NA, in September. This equipment is expected to have a prototype by the end of this year and officially enter production next year.

TSMC’s Mass Production of 2nm by 2025

This year, TSMC has unveiled its latest advanced semiconductor manufacturing roadmap in various locations, including Santa Clara, California, and Taiwan. The roadmap covers a range of processes from 3nm to 2nm.

TSMC’s current roadmap for 3nm includes N3, N3E, N3P, N3X, and N3 AE, with N3 serving as the foundational version, N3E as an enhanced version with further cost optimization, N3P focusing on improved performance with a planned start in the second half of 2024, N3X targeting high-performance computing devices with a mass production goal in 2025, and N3 AE designed specifically for the automotive sector, offering greater reliability and the potential to shorten time-to-market by 2-3 years.

In the 2nm realm, TSMC is planning to achieve mass production of the N2 process by 2025. TSMC has reported that the N2 process will offer a 15% speed improvement over N3E at the same power or a 30% reduction in power consumption, with a 15% increase in transistor density. In September, media reports revealed that TSMC has formed a task force to accelerate 2nm pilot production and mass production, aiming for risk production next year and official mass production in 2025.

To ensure the smooth development of 2nm process technology, TSMC has initiated efforts in the upstream equipment sector. On September 12th, TSMC announced the acquisition of a 10% stake in IMS Nanofabrication, a subsidiary of Intel, for a price not exceeding $432.8 million. IMS specializes in the research and production of electron beam lithography machines, which find extensive applications in semiconductor manufacturing, optical component manufacturing, MEMS manufacturing, and more. The industry sees TSMC’s IMS acquisition as vital for developing crucial equipment and meeting the demand for 2nm process commercialization.

(Image: Intel)

Reports indicate that the United States is poised to unveil an updated set of restrictions on chip exports to China this week. Beyond the previously reported tightening measures on AI chips and equipment exports, these new regulations are expected to restrict the supply to chip design companies. The aim is to enhance control over the sale of graphic chips and advanced chip manufacturing equipment for AI applications to Chinese enterprises, with the possibility of adding Chinese chip design companies to the list of restricted entities.

As reported from Reuters and Bloomberg, U.S. authorities will demand that overseas manufacturers obtain licenses to fulfill orders from these companies and subject Chinese firms attempting to circumvent restrictions by using third-party countries for shipping to additional inspections. While the new regulations are expected to be announced this week, the potential for delays should not be ruled out.

In October 2022, the United States declared export restrictions on advanced semiconductor processes and chip manufacturing equipment bound for China, as a measure to prevent the development of cutting-edge technology that could potentially bolster military capabilities for geopolitical adversaries.

Following the implementation of these export bans, U.S. tech companies, such as Nvidia and Applied Materials, incurred significant losses in orders. For example, Nvidia was unable to sell its two most advanced AI chips to Chinese companies, leading to the introduction of a “downgraded” chip, the H800, designed specifically for the Chinese market to bypass existing regulations.

U.S. officials have revealed plans to introduce new guidelines for AI chips, including the restriction of certain advanced data center AI chips that currently do not fall under any limitations. They are considering the removal of “bandwidth parameters” to prevent the entry of AI chips perceived as too powerful into China.

However, they plan to introduce expanded guidelines for chip control, which may reduce communication speeds among AI chips. Slower communication could increase the complexity and cost of AI development, particularly when many chips need to be connected for training large AI models. Additionally, the U.S. will introduce “performance density parameters” to guard against potential future workarounds by companies.

Reports suggest that the United States is looking to prohibit the export of Nvidia’s H800 chip, a “downgraded” chip designed for the Chinese market to legally bypass existing regulations.

The Biden administration is also preparing for additional scrutiny of Chinese companies attempting to modify shipping and manufacturing locations in a bid to evade specific country restrictions. This rule will continue to limit sales of specific chips to Chinese companies through overseas subsidiaries and related entities, requiring authorization before exporting restricted technology to countries that could serve as intermediaries.

Furthermore, the progress in Huawei’s new smartphones has prompted the U.S. authorities to tighten control further, initiating investigations for actions against Huawei or SMIC that will be carried out independently of the new export control regulations.

In response to the anticipated expansion of U.S. export controls on Chinese companies, Chinese Foreign Ministry Spokesperson Mao Ning stated, “We have made our position clear on US restrictions of chip exports to China. The US needs to stop politicizing and weaponizing trade and tech issues and stop destabilizing global industrial and supply chains. We will closely follow the developments and firmly safeguard our rights and interests.”

(Image: Nvidia)

As TSMC’s earnings call approaches, the market is abuzz with rumors that the company may revise down its capital expenditure target for this year. This potential adjustment is believed to be driven by delays in Intel’s 3-nanometer outsourcing and the deferral of the production schedule for TSMC’s 4-nanometer US fab. The initial capital expenditure target, which was close to the $32 billion to $36 billion range, may now be lowered to below $30 billion, marking its lowest point in nearly three years.

According to Taiwan’s Economic Daily, TSMC has refrained from commenting on these speculations. Even if TSMC does adjust its capital expenditure for this year, industry sources suggest that the company will increase its annual R&D expenses, continuing its commitment to advanced research and development.

In recent years, TSMC has rapidly expanded its capital expenditure, reaching a record high of $36.3 billion last year. In the first half of this year, the actual capital expenditure amounted to $18.11 billion, including $8.17 billion in the second quarter, slightly down from the $9.94 billion in the first quarter.

During their July earnings conference, TSMC stated that their capital expenditure for the year would remain in the range of $32 billion to $36 billion. However, considering market dynamics, the actual expenditure for the full year is expected to be towards the lower end of this range.

The latest reports suggest that due to the delays in Intel’s 3-nanometer outsourcing and the postponement of the 4-nanometer production schedule at the US fab, approximately $4 billion originally earmarked for this year’s capital expenditure may be postponed until next year, resulting in capital expenditure for this year falling below $30 billion. As for next year’s capital expenditure, it may remain on par with this year.

ASML, a leading supplier of semiconductor lithography equipment, previously revealed in its July earnings conference that there were delays in shipments of EUV equipment due to installation delays at customer factories. However, ASML maintained a robust order backlog and expects overall performance to continue growing in 2024.

Industry experts believe that the “installation delays” mentioned by ASML at that time were related to TSMC, and because of the delay in EUV equipment installation, TSMC’s capital expenditure for this year may be deferred accordingly.

Analysts in the industry suggest that if we consider TSMC’s earlier projection of capital expenditure falling within the $32 billion to $36 billion range, and subtract the actual expenses incurred in the first half of the year, the capital expenditure for the second half of the year could see a decline, estimated to be around $13.89 billion or more. If the postponement rumors materialize, second-half capital expenditure might fall below $10 billion.

TSMC Founder Morris Chang, speaking at a press conference following the TSMC sports event on the 14th, noted that countries around the world are currently building their semiconductor supply chains. In his view, Japan is a more ideal location for this, given the evolving economic landscape, Taiwan’s semiconductor manufacturing environment might lose its advantages in about 20 to 30 years.

According to a report by Taiwanese media TechNews, discussing TSMC’s global presence, Chang mentioned that about 27 to 28 years ago, it was his dream to build a TSMC fab in the United States, and at that time, establishing WaferTech was a beautiful dream. However, this dream turned into a nightmare after 2 to 3 years due to various cultural factors. But he also believes that today’s TSMC is vastly different from the company of a couple of decades ago. Whether it’s talent or technology, it has improved significantly. With proper preparation, perhaps the past dream can be realized.

Now, countries worldwide are establishing their semiconductor supply chains. So which countries have a better chance of success? Chang believes, based on past experiences, that Japan and Singapore are more ideal places. However, Singapore has limited resources, making Japan the more favorable option. Additionally, the Kyushu region in Japan offers abundant resources such as land, water, and electricity, along with a strong work culture.

Looking at TSMC’s overseas expansion, in 2020, TSMC announced its investment to build a factory in Arizona, USA, with plans to establish 4-nanometer process capabilities. Construction on the Arizona plant began in June 2021, and a groundbreaking ceremony was held in December of the same year. However, due to construction delays, the actual start of production is expected to be pushed back from the original target of late 2024 to 2025.

In comparison, TSMC’s Kumamoto fab has commenced equipment installation, and its facility progress seems to be ahead of the new plant in Arizona. In addition to their Kumamoto Fab 1, TSMC had previously indicated its consideration of building a second factory in Japan, likely to be situated near the first one.

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(Photo credit: TSMC)

On October 11th, Amkor announced the official opening of its factory located in the Yen Phong 2C Industrial Park in Bac Ninh Province, Vietnam. The new facility, occupying 57 acres, is set to become Amkor’s largest, with an investment of approximately $1.6 billion by 2035. The factory primarily focuses on providing advanced system-level packaging and testing solutions to meet the semiconductor industry’s demand for advanced packaging. However, the company has not disclosed the factory’s current production and capacity.

Multiple Players Pursue CoWoS

The ongoing AI trend continues to drive demand for Chip-on-Wafer-on-Substrate (CoWoS) technology, benefiting TSMC, which holds a significant share of CoWoS production orders. However, companies like ASE Group, Amkor, and UMC are also positioning themselves in the CoWoS packaging manufacturing space. Industry experts believe that given the current high demand for TSMC’s CoWoS production, part of this demand may potentially shift to Amkor’s factories.

Furthermore, the popular Nvidia AI chips, which are in high demand globally, utilize 2.5D packaging technology, a responsibility currently held by TSMC. Recently, Nvidia hinted at the mass production of new AI chips like the GH200 and general server chip L40S, with reports suggesting that L40S will not require 2.5D packaging. Instead, it will be shared among several backend packaging companies, including ASE, Amkor, and SPIL.

Industry source has noted the strong demand for CoWoS in the AI sector, and with TSMC’s CoWoS production capacity already unable to meet demand for several quarters, some demand may potentially shift to Amkor or Samaung’s facilities.

Amkor has announced plans to expand its advanced packaging CoWoS-like capacity. According to industry insiders, Amkor’s monthly production capacity for 2.5D advanced packaging is expected to reach approximately 3,000 wafers in early 2023, with estimates of reaching 5,000 wafers by the end of 2023 and aiming for a significant increase to 7,000 units by the end of 2024.

Additionally, ASE Group has announced its presence in advanced CoWoS-related packaging. With their fan-out chip-on-substrate (FOCoS-Bridge) packaging technology, ASE has been chosen by major chip design house to handle their backend packaging after CoW.

In mid-September, South Korean media reported that Samsung is set to introduce its FO-PLP 2.5D advanced packaging technology to catch up with TSMC in the field of advanced packaging for AI chips. Samsung’s Advanced Packaging (AVP) team began developing FO-PLP advanced packaging for 2.5D chip packaging, allowing the integration of System-on-Chip (SoC) and High Bandwidth Memory (HBM) into an interposer to create a complete chip.

It’s worth mentioning that Samsung’s FO-PLP 2.5D packaging is rectangular, while TSMC’s CoWoS 2.5D uses a circular substrate. Samsung’s FO-PLP 2.5D packaging avoids edge substrate losses and boasts higher production efficiency. However, due to the need to transplant chips from wafers onto rectangular substrates, the process is more complex.

CoWoS Demand Continues

CoWoS technology is a form of 2.5D and 3D packaging, where chips are stacked and then packaged onto a substrate, resulting in a 2.5D or 3D structure. This technology reduces chip space, while also decreasing power consumption and costs. CoWoS packaging is applied in high-performance computing, artificial intelligence, data centers, 5G, the Internet of Things, automotive electronics, and other fields.

TrendForce research indicates a growing demand for advanced packaging technologies for AI and HPC chips. Currently, TSMC’s CoWoS is the primary choice for AI server chip production. CoWoS packaging mainly consists of CoW (Chip on Wafer), integrating various logic ICs (such as CPUs, GPUs, ASICs, etc.) and HBM memory, while oS (On Substrate) integrates CoW elements using Solder bump interconnects and packages them on a substrate. These CoWoS packages become the primary computing units on server motherboards, together with other components like networks, storage, power supply units (PSUs), and other I/O units, forming complete AI server systems.

Explore more

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(Photo credit: Amkor)