Equipment is playing an indispensable role during the wafer manufacturing process. In response to market needs, the global EUV lithography supplier, ASML, has recently taken significant steps.

ASML’s Bold Move: Annual Investment of EUR 100 Million in Berlin Plant

As reported by the German media “Handelsblatt,” the Netherlands-based company ASML plans to invest EUR 100 million (USD 109 million) in 2023, with a similar annual investment in the subsequent years. This investment aims to enhance the production and development capabilities of ASML’s manufacturing plant located in Berlin, Germany.

Reports indicate that ASML’s Berlin plant primarily produced core components of EUV equipment, including wafer clamps, wafer tables, reticle chucks and mirror blocks. ASML acquired this facility, known as “Berliner Glas,” in 2020.

Foundries Actively Pursue EUV equipment

The EUV equipment plays a crucial role in manufacturing, utilizing specific wavelength light for radiation to precisely imprint images on wafers. Currently, the EUV equipment market is highly concentrated, with only a few global companies mastering this technology. Among them, Dutch company ASML stands out as the world’s largest and most advanced EUV company. Additionally, companies like Nikon, Canon, and Shanghai Micro Electronics Equipment (SMEE) are strategically positioning themselves in the EUV sector.

EUV technology, used for exposing semiconductor process, is indispensable due to its high cost, complex processes, and limited supply. ASML is the sole global supplier of EUV. For advanced processes below 7nm, EUV serves as an essential device. Developed over more than 20 years, EUV technology has become the cornerstone of advanced processes, enabling the continuation of Moore’s Law for at least another decade.

As a crucial EUV equipment supplier, ASML is working on a new generation of NA-EUV equipment, where “NA” represents numerical aperture. A higher NA value means a higher achievable resolution, allowing for more transistors on the chip. It is expected that by the year-end, ASML will unveil the world’s first high-NA EUV and deliver it to Intel.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

TSMC’s 2nm process will continue to leverage EUV technology. In a previous announcement in September, TSMC disclosed the acquisition of Intel’s subsidiary IMS for up to US 432.8 million, focusing on the research and production of electron beam lithography machines. Industry experts believe that TSMC’s move ensures the technical development of critical equipment and meets the supply demand for the commercialization of 2nm.

Following 2nm chips. Samsung plans to achieve mass production of 2nm processes in the mobile field by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively. According to the report in September, Samsung is gearing up to secure the yield of the next-generation EUV equipment, High-NA, with the prototype expected to launch later this year and official supply next year.

After announcing its return to the foundry business, Intel revealed in October that it has commenced mass production of Intel 4 process nodes using EUV technology. Currently, both Intel 7 and Intel 4 have achieved mass production, and Intel 3 is progressing according to plan, with the goal of completion by the end of 2023.

(Image: ASML)

According to TechNews’ report, there are recent rumors indicating that AMD’s next-generation chip, with the Zen5C architecture codenamed “Prometheus,” will adopt a “Dual Foundry Mode.” This means it will simultaneously utilize TSMC’s 3nm and Samsung’s 4nm processes. This move suggests that AMD aims to diversify chip manufacturing, avoiding reliance solely on TSMC for its upcoming products.

Industry sources suggest that factors such as geopolitical considerations, negotiation tactics, and the overall semiconductor manufacturing ecosystem drive the search for secondary sources. AMD’s decision to employ a dual foundry approach is likely a strategic move to mitigate risks in this dynamic landscape.

Reportedly, Samsung’s 4nm process will primarily be utilized for the base version of Prometheus, while TSMC’s 3nm process will be employed for the high-end variant of Prometheus.

EXTREMETECH finds AMD’s move intriguing, speculating that it might stem from uncertainty about sourcing all chips exclusively from TSMC. This is significant for Samsung, historically excluded from the consumer tech and gaming sector. Since NVIDIA switched from Samsung to TSMC for the production of Ampere GPUs using the 8nm process, Samsung has been left out of the equation.

If the collaboration between AMD and Samsung proves successful, other companies may also consider shifting to Samsung. Reports suggest that AMD’s choice of Samsung’s 4nm process over the 3nm process could be attributed to potential yield challenges.

While it’s uncertain whether AMD will indeed implement the “Dual Foundry Mode,” the anticipation for the Zen5 architecture next year is high. Samsung is currently ahead of the industry in the adoption of GAA (Gate-All-Around) technology for its manufacturing processes, introducing GAA technology with their 3nm process ahead of others in the industry. TSMC, on the other hand, is anticipated making a similar change no earlier than 2025.

Read more

• [News] A battle on 4nm: AMD Teams Up with Samsung, while Google Weighs Supplier Split

(Photo credit: AMD)

The growing importance of advanced processes in wafer foundries is evident, propelled by innovations like AI and high-performance computing. While 3nm chips have entered the consumer market, efforts are underway in wafer foundries to advance to 2nm chips. Recent reports suggest progress in 1nm chips, further fueling the competition among wafer foundries.

2nm Chips: Unveiling in 2025

Anticipated by 2025, the race for 2nm chips is in full swing, with major players like TSMC, Samsung, and Rapidus actively pursuing mass production. TSMC plans to implement GAAFET transistors in its 2nm process by 2025, offering a 15% speed boost and up to a 30% reduction in power consumption compared to N3E, all while increasing chip density by over 15%.

Samsung is on a similar trajectory, planning to unveil its 2nm process by the end of 2025. As report by media in October, Samsung Foundry, said on Semiconductor Expo 2023 in South Korea, has already initiated discussions with major clients, expecting decisions in upcoming future.

Rapidus aims for trial production of 2nm chips in 2025, scaling up to mass production by 2027. Reports in September indicated that ASML plans to establish a technical support hub in Hokkaido, Japan in 2024. Approximately 50 engineers will be dispatched to Rapidus’ ongoing construction site for the 2nm plant, assisting in the setup of EUV lithography equipment on the trial production line, and providing support for factory activation, maintenance, and inspections.

When will 1nm chip arrive?

Apart from 2nm, the industry’s attention turns to 1nm-level chips. According to industry plans, mass production of 1nm-level chips is expected between 2027 and 2030.

Nikkei recently reveals collaboration between Japanese chipmaker Rapidus, Tokyo University, and the French technological research organization Leti to develop foundational technology for 1nm IC design. Talent exchange and technical sharing are slated to begin in 2024, aiming to establish a supply system for indispensable 1nm chip products, crucial for enhancing auto driving and AI performance.

On the other hand, collaborations with IBM for 1nm products are also being considered. The computing performance of 1nm products, anticipated to become mainstream in the 2030s, is expected to surpass 2nm by 10-20%.

TSMC and Samsung are also eyeing 1nm chip development. TSMC’s initial plan to build a 1.4nm process wafer fab in Taiwan faced delays after abandoning the original site selection in October. Samsung aims to launch its 1.4nm process by the end of 2027, with improved performance and power consumption through an increased number of nanosheets per transistor, promising enhanced control over current flow and reduced power leakage.

(Image: TSMC)

Against the backdrop of geopolitical influences, the concentration of advanced semiconductor manufacturing processes in Taiwan has raised concerns among international companies. According to TrendForce data, as of the end of 2024, over 70% of global advanced process manufacturing capacity is still located in Taiwan.

Governments worldwide have responded by offering generous subsidy policies to attract semiconductor foundries to establish plants locally. The dynamics of Taiwan’s semiconductor fabs in the global setting and changes in the global production landscape have become a focal point of industry attention.

Per TrendForce’s data, when considering the equivalent 12-inch wafer production capacity, in 2023, Taiwan held a global share of approximately 47%, followed by China at 26%, South Korea at 12%, the United States at 6%, Singapore at 4%, Japan at 2%, Germany at 1%, and others at 2%. By 2027, the distribution is expected to shift, with Taiwan’s share decreasing to 42%, China increasing to 28%, South Korea at 10%, the United States at 7%, Singapore at 6%, Japan at 3%, Germany at 2%, and others at 1%.

Examining recent developments in the overseas expansion of Taiwan’s semiconductor foundries, Powerchip Semiconductor Manufacturing Corporation (PSMC) has officially announced the establishment of its first 12-inch fab, JSMC, in Sendai, Miyagi Prefecture, Japan. According to TrendForce’s research, the plant is planned to have a total capacity of around 40Kwspm, starting with a 40nm node and gradually transitioning to 28nm, primarily serving domestic clients in Japan while seeking subsidies and tax incentives for semiconductor.

JSMC’s construction is scheduled to commence in 2024, with full-scale production expected by 2027. With the establishment of PSMC’s overseas fab, TrendForce estimates that PSMC’s overseas production capacity will grow from 0% in 2023 to 9% in 2027.

The progress of TSMC’s second fab in Kumamoto, Japan, has garnered significant industry attention recently. On another note, The German cartel office has approved Bosch, NXP, and Infineon’s investment in TSMC’s German fab, ESMC. Each company will acquire a 10% stake, while TSMC will retain substantial control with over 50% ownership.

According to TrendForce’s research, ESMC’s total planned capacity is around 40Kwspm, focusing on 28/22nm and 16/12nm processes, with construction expected to start in the second half of 2024 and mass production in 2027. TrendForce predicts that TSMC’s overseas production capacity will increase from 9% in 2023 to 15% in 2027.

As for UMC, TrendForce’s research indicates that the overseas production capacity is projected to increase from 42% in 2023 to approximately 47% by 2027. Additionally, UMC’s Fab12i in Singapore has a production capacity of approximately 60Kwspm, with plans for manufacturing processes ranging from 55/40nm to 28/22nm. Moreover, UMC’s Fab12M in Japan is expanding its capacity by around 10Kwspm in collaboration with Denso.

Regarding Vanguard International Semiconductor (VIS), it was previously reported by Nikkei that VIS plans to construct its first 12-inch wafer fab in Singapore, primarily focusing on the demand for automotive chips. However, VIS has not yet officially announced any related developments. According to TrendForce’s research, if VIS does not have new plans for investment in a 12-inch fab, its estimated spending required for the operation of various fabs in 2024 is approximately $94 million, representing a nearly 70% decrease compared to previous years.

Explore more

• TrendForce Foresees China’s Mature Wafer Processes to Expand to 33% by 2027, Japan Secures Advanced Processes
• China’s Wafer Fabs Hits 44 with Future Expansion 32, Mainly Targeting on The Mature Process

The demand for TSMC’s CoWoS advanced packaging is skyrocketing. Following NVIDIA’s expansion confirmation in October, there are reports in the industry that major clients like Apple, AMD, Broadcom, Marvell, and others are also placing additional orders with TSMC.

To meet the demands of these five major clients, TSMC is fast-tracking the expansion of CoWoS advanced packaging capacity. Next year, the monthly capacity will increase by about 20% more than the original doubling target, reaching 35,000 wafers, reported by UDN News.

TSMC has not commented on the capacity deployment for CoWoS advanced packaging. Industry sources believe that the substantial orders from TSMC’s major clients indicate a widespread growth in AI applications, driving the demand for chips such as GPU and AI accelerators.

In response to the continuous increase in AI demand, TSMC had previously announced the doubling of CoWoS advanced packaging capacity expansion for next year but did not disclose the monthly production capacity. Industry reports suggest that TSMC’s CoWoS advanced packaging capacity next year will not only double but will also increase by an additional 20% from the original target, resulting in a total monthly capacity of 35,000 wafers.

NVIDIA currently stands as the main large customer for TSMC’s CoWoS advanced packaging, securing almost 60% of TSMC’s related capacity, which is used in its AI chips such as H100 and A100. Additionally, AMD’s latest AI chip products are in the mass production stage, and the upcoming MI300 chip, expected to launch next year, will adopt both SoIC and CoWoS advanced packaging.

At the same time, Xilinx, a subsidiary of AMD, has been a significant customer for TSMC’s CoWoS advanced packaging. With the continuous growth in AI demand, not only Xilinx but also Broadcom has started increasing orders for TSMC’s CoWoS advanced packaging capacity.

(Image: TSMC)

Explore more

• [News] TSMC Deploys Manpower to Support Longtan and Tainan Facilities Amid CoWoS and 3nm Demand
• Exploring the Significance of 3D-SOC and 3D-IC in Cutting-Edge 3D Advanced Packaging