The AI landscape witnesses a robust surge with the consecutive launches of AMD’s “Instinct MI300” series AI chips and NVIDIA’s upcoming “B100” GPU structure. This wave of innovation propels a flourishing demand for AI-related Outsourced Semiconductor Assembly And Test Services (OSAT), surpassing initial estimates by over 10%. OSAT companies like ASE Holdings, King Yuan Electronics (KYEC), and Sigurd are poised to experience a notable uptick in revenue, as reported by UDN News.

According to reports, AMD is launching the “Instinct MI300” series AI chips this week, and NVIDIA plans to unveil the next-gen “B100” GPU next year. This successive release of new AI products by the two giants is boosting momentum in related OSATs collaboration.

NVIDIA is gearing up for the 2024 launch of its next-gen Blackwell architecture B100 GPU, saying AI performance exceeding twice that of the H200 GPU under the Hopper architecture, signifying a substantial leap in computational prowess.

Positive Outlook in 2024 for OSATs Amid AI Chip Development

Industry source indicates that due to the AI extensive computation requirements, advanced packaging is gradually becoming mainstream. This involves stacking chips and packaging them on a substrate. Depending on the arrangement, it is divided into 2.5D and 3D packaging. The advantage of this packaging technology is the ability to reduce chip space while also reducing power consumption and costs.

It is said the surge in AI chip orders from AMD and NVIDIA has led to a bottleneck in TSMC CoWoS advanced packaging capacity. This unexpected demand has exceeded projections for related OSATs, including ASE Holdings, KYEC, and Sigurd.

In the case of ASE Holdings, its subsidiary Siliconware Precision Industries (SPIL) possesses the advanced packaging capacity essential for generative AI chips. Joseph Tung, CFO of ASE Holdings, notes that while AI currently in its early-stage and is set to drive explosive growth. As AI integrates into existing and new applications, the demand for advanced packaging is expected to fuel the industry’s entry into the next super growth cycle.

For KYEC, a significant expansion in AI chip testing capacity since Q2 this year positions the company to benefit from the surge in demand.

Sigurd’s COO Tsan-Lien Yeh addresses that, with the release of AI phones, recognizing the doubled testing time for phone chips, which now carry APU/NPU for AI computing compared to general 5G chips. Sigurd has upgraded its equipment to align with future customer needs.

(Image: ASE VIPack’s video)

According to TechNews’ report, Apple, NVIDIA, AMD, Qualcomm, and MediaTek all utilize TSMC’s semiconductor processes for manufacturing their latest chips, with some potentially employing Samsung’s foundry, though typically not for flagship products.

With Samsung’s improved yield rates in recent months, the company is eager to secure a portion of the orders, particularly for the 3-nanometer GAA (Gate-All-Around) process.

Earlier market reports suggested that Qualcomm’s Snapdragon 8 Gen 4 might adopt a dual-foundry strategy, simultaneously utilizing TSMC’s N3E process technology and Samsung’s SF3E process technology.

However, both Qualcomm and MediaTek currently plan to employ TSMC’s second-generation 3-nanometer process technology (N3E) for manufacturing chips like the Snapdragon 8 Gen 4 and Dimensity 4, without pursuing a dual-foundry strategy at this time.

As of the end of June 2022, Samsung announced the commencement of production for 3-nanometer process chips at its Hwaseong Industrial Complex in South Korea. These chips incorporate a new GAA transistor architecture technology, rumored to be more energy-efficient compared to TSMC’s 3-nanometer FinFET technology. Despite this, in the realm of 3nm, Samsung has yet to secure substantial orders from major clients.

Interestingly, the company has seen more success in the 4nm domain. It is reported that Samsung has gradually addressed yield and various issues in the 4-nanometer process technology domain. The third generation of 4-nanometer process technology has seen improvements in performance, reduced power consumption, increased density, and achieved yields close to TSMC’s level. Market sources indicate that Samsung has gained recognition from companies like AMD and Tesla, securing new orders.

Currently, TSMC’s 3-nanometer process technology production capacity is ramping up, with an expected monthly capacity of 100,000 wafers by the end of 2024. The revenue contribution is projected to increase from the current 5% to 10%.

Meanwhile, Samsung plans to introduce the second generation of its 3-nanometer process technology, named SF3 (3GAP), in 2024. Building upon the existing SF3E, it aims for further optimization, and Samsung’s in-house Exynos 2500 is expected to be one of the first high-performance chips to adopt this new process technology.

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Equipment is playing an indispensable role during the wafer manufacturing process. In response to market needs, the global EUV lithography supplier, ASML, has recently taken significant steps.

ASML’s Bold Move: Annual Investment of EUR 100 Million in Berlin Plant

As reported by the German media “Handelsblatt,” the Netherlands-based company ASML plans to invest EUR 100 million (USD 109 million) in 2023, with a similar annual investment in the subsequent years. This investment aims to enhance the production and development capabilities of ASML’s manufacturing plant located in Berlin, Germany.

Reports indicate that ASML’s Berlin plant primarily produced core components of EUV equipment, including wafer clamps, wafer tables, reticle chucks and mirror blocks. ASML acquired this facility, known as “Berliner Glas,” in 2020.

Foundries Actively Pursue EUV equipment

The EUV equipment plays a crucial role in manufacturing, utilizing specific wavelength light for radiation to precisely imprint images on wafers. Currently, the EUV equipment market is highly concentrated, with only a few global companies mastering this technology. Among them, Dutch company ASML stands out as the world’s largest and most advanced EUV company. Additionally, companies like Nikon, Canon, and Shanghai Micro Electronics Equipment (SMEE) are strategically positioning themselves in the EUV sector.

EUV technology, used for exposing semiconductor process, is indispensable due to its high cost, complex processes, and limited supply. ASML is the sole global supplier of EUV. For advanced processes below 7nm, EUV serves as an essential device. Developed over more than 20 years, EUV technology has become the cornerstone of advanced processes, enabling the continuation of Moore’s Law for at least another decade.

As a crucial EUV equipment supplier, ASML is working on a new generation of NA-EUV equipment, where “NA” represents numerical aperture. A higher NA value means a higher achievable resolution, allowing for more transistors on the chip. It is expected that by the year-end, ASML will unveil the world’s first high-NA EUV and deliver it to Intel.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

TSMC’s 2nm process will continue to leverage EUV technology. In a previous announcement in September, TSMC disclosed the acquisition of Intel’s subsidiary IMS for up to US 432.8 million, focusing on the research and production of electron beam lithography machines. Industry experts believe that TSMC’s move ensures the technical development of critical equipment and meets the supply demand for the commercialization of 2nm.

Following 2nm chips. Samsung plans to achieve mass production of 2nm processes in the mobile field by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively. According to the report in September, Samsung is gearing up to secure the yield of the next-generation EUV equipment, High-NA, with the prototype expected to launch later this year and official supply next year.

After announcing its return to the foundry business, Intel revealed in October that it has commenced mass production of Intel 4 process nodes using EUV technology. Currently, both Intel 7 and Intel 4 have achieved mass production, and Intel 3 is progressing according to plan, with the goal of completion by the end of 2023.

(Image: ASML)

According to TechNews’ report, there are recent rumors indicating that AMD’s next-generation chip, with the Zen5C architecture codenamed “Prometheus,” will adopt a “Dual Foundry Mode.” This means it will simultaneously utilize TSMC’s 3nm and Samsung’s 4nm processes. This move suggests that AMD aims to diversify chip manufacturing, avoiding reliance solely on TSMC for its upcoming products.

Industry sources suggest that factors such as geopolitical considerations, negotiation tactics, and the overall semiconductor manufacturing ecosystem drive the search for secondary sources. AMD’s decision to employ a dual foundry approach is likely a strategic move to mitigate risks in this dynamic landscape.

Reportedly, Samsung’s 4nm process will primarily be utilized for the base version of Prometheus, while TSMC’s 3nm process will be employed for the high-end variant of Prometheus.

EXTREMETECH finds AMD’s move intriguing, speculating that it might stem from uncertainty about sourcing all chips exclusively from TSMC. This is significant for Samsung, historically excluded from the consumer tech and gaming sector. Since NVIDIA switched from Samsung to TSMC for the production of Ampere GPUs using the 8nm process, Samsung has been left out of the equation.

If the collaboration between AMD and Samsung proves successful, other companies may also consider shifting to Samsung. Reports suggest that AMD’s choice of Samsung’s 4nm process over the 3nm process could be attributed to potential yield challenges.

While it’s uncertain whether AMD will indeed implement the “Dual Foundry Mode,” the anticipation for the Zen5 architecture next year is high. Samsung is currently ahead of the industry in the adoption of GAA (Gate-All-Around) technology for its manufacturing processes, introducing GAA technology with their 3nm process ahead of others in the industry. TSMC, on the other hand, is anticipated making a similar change no earlier than 2025.

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• [News] A battle on 4nm: AMD Teams Up with Samsung, while Google Weighs Supplier Split

(Photo credit: AMD)

The growing importance of advanced processes in wafer foundries is evident, propelled by innovations like AI and high-performance computing. While 3nm chips have entered the consumer market, efforts are underway in wafer foundries to advance to 2nm chips. Recent reports suggest progress in 1nm chips, further fueling the competition among wafer foundries.

2nm Chips: Unveiling in 2025

Anticipated by 2025, the race for 2nm chips is in full swing, with major players like TSMC, Samsung, and Rapidus actively pursuing mass production. TSMC plans to implement GAAFET transistors in its 2nm process by 2025, offering a 15% speed boost and up to a 30% reduction in power consumption compared to N3E, all while increasing chip density by over 15%.

Samsung is on a similar trajectory, planning to unveil its 2nm process by the end of 2025. As report by media in October, Samsung Foundry, said on Semiconductor Expo 2023 in South Korea, has already initiated discussions with major clients, expecting decisions in upcoming future.

Rapidus aims for trial production of 2nm chips in 2025, scaling up to mass production by 2027. Reports in September indicated that ASML plans to establish a technical support hub in Hokkaido, Japan in 2024. Approximately 50 engineers will be dispatched to Rapidus’ ongoing construction site for the 2nm plant, assisting in the setup of EUV lithography equipment on the trial production line, and providing support for factory activation, maintenance, and inspections.

When will 1nm chip arrive?

Apart from 2nm, the industry’s attention turns to 1nm-level chips. According to industry plans, mass production of 1nm-level chips is expected between 2027 and 2030.

Nikkei recently reveals collaboration between Japanese chipmaker Rapidus, Tokyo University, and the French technological research organization Leti to develop foundational technology for 1nm IC design. Talent exchange and technical sharing are slated to begin in 2024, aiming to establish a supply system for indispensable 1nm chip products, crucial for enhancing auto driving and AI performance.

On the other hand, collaborations with IBM for 1nm products are also being considered. The computing performance of 1nm products, anticipated to become mainstream in the 2030s, is expected to surpass 2nm by 10-20%.

TSMC and Samsung are also eyeing 1nm chip development. TSMC’s initial plan to build a 1.4nm process wafer fab in Taiwan faced delays after abandoning the original site selection in October. Samsung aims to launch its 1.4nm process by the end of 2027, with improved performance and power consumption through an increased number of nanosheets per transistor, promising enhanced control over current flow and reduced power leakage.

(Image: TSMC)