According to a report by China’s media outlet Jiwei, Japanese officials recently released a photo of a meeting with Chairman Mark Liu of TSMC. Japan’s Minister of Economy, Trade, and Industry, Yasutoshi Nishimura, updated his personal X account on the 1st of the month and posted a photo of the meeting. In his post, he mentioned the meeting with Mark Liu and the progress at the Kumamoto factory.

“We had a meeting with Chairman Mark Liu of TSMC,” wrote Yasutoshi Nishimura on X. “TSMC, in collaboration with Sony and Denso through their joint venture JASM, is constructing a factory in Kumamoto as a critical national initiative to revitalize Japan’s semiconductor industry. Cooperation in Kumamoto is making progress, and Japanese materials and equipment manufacturers, along with other related companies, have announced new investments. We will continue to collaborate for future innovations.”

The JASM Kumamoto factory, which began construction in 2022, started using its office building in August of this year. Hundreds of employees have been gradually moving in, and from October, machinery and equipment will be progressively installed. The earliest small-scale trial production is expected in the second quarter of 2024, with full-scale production by the end of the year. The monthly production capacity will reach 45,000 12-inch wafers, and TSMC is not ruling out the possibility of expanding with a second Kumamoto factory.

Sources confirm that a group of TSMC equipment-related engineers has recently quietly arrived in Japan. They have received orientation materials officially starting work at the TSMC Kumamoto factory.

Industry sources suggest that TSMC is on track to achieve its goal of starting production at the Kumamoto factory by the end of next year, and possibly even ahead of schedule.

台湾のマーク・リュウTSMC会長と会談しました。熊本におけるTSMCとソニー・デンソー合弁会社JASMの工場建設は、日本の半導体産業の再興に向けた重要な国家プロジェクトです。熊本では、日本の素材・装置メーカーなど関連企業が続々と新しい投資を表明するなど連携が進んでいます。今後も将来のイノベー… pic.twitter.com/zAIYxiDESa

— 西村やすとし NISHIMURA Yasutoshi (@nishy03) October 1, 2023

(Photo credit: TSMC)

According to a report by Taiwan’s Economic Daily, TSMC is set to hold its Q3 earnings conference on October 19th. The market is eagerly anticipating insights from the company’s top executives on six key areas: the latest semiconductor market outlook, Q3 financial forecasts, the status of 3-nanometer chip orders, progress in advanced packaging expansion, capital expenditure updates, and the latest developments in the AI market.

During the conference, TSMC will also unveil its financial results for the previous quarter. Analysts are expecting TSMC’s Q3 consolidated revenue, when measured in USD, to grow by nearly 10%, with a chance of gross margin exceeding the company’s estimated median of 52.5%. This suggests that Q3 profits are likely to surpass those of Q2.

TSMC has already announced its combined revenue for July and August, which totaled NT$366.3 billion. Based on TSMC’s financial forecasts, Q3 consolidated revenue is expected to reach between $16.7 billion and $17.5 billion USD. Using an exchange rate of 30.8 NT dollars per USD, this translates to an expected consolidated revenue in NT dollars ranging from NT$514.4 billion to NT$539 billion.

In the first half of the year, TSMC’s capital expenditure was $9.94 billion in Q1 and $8.17 billion in Q2, totaling $18.11 billion. Securities analysts previously estimated that TSMC’s annual capital expenditure for this year could range from $32 billion to $36 billion USD, with the possibility of a decrease next year.

Some industry experts believe that as advanced manufacturing processes have advanced to 2 nanometers, the customer base for the latest processes has started to decrease. Looking at the 3-nanometer process that is already in mass production, only Apple is currently leading the adoption, while others like NVIDIA, Qualcomm, and MediaTek are expected to transition to the 3-nanometer process next year. As a result, TSMC is shifting its focus to expanding production in the more cost-effective advanced packaging sector, which is one of the key reasons for the decrease in TSMC’s capital expenditure.

Furthermore, TSMC is currently estimating that it will be the first to introduce an enhanced version of the 3-nanometer process next year, with expectations to transition to the 2-nanometer process by 2025, using a new Gate-All-Around (GAA) transistor architecture to replace the FinFET transistor architecture used for nearly a decade. This represents a significant step into a new generation of semiconductor technology. Additionally, capacity for advanced packaging is expected to double next year.

(Photo credit: TSMC)

According to Taiwan’s Economic Daily, after disassembling Huawei’s Mate 60 Pro smartphone, it has been revealed that the chips, including the Kirin 9000S, are produced by China’s semiconductor foundry, SMIC, using their advanced 7-nanometer process. This development has brought attention to SMIC’s manufacturing capabilities. Recently, it has been reported that SMIC has placed a substantial order with Taiwanese suppliers in the supply chain, equivalent to approximately two years’ worth of demand, and is urging swift delivery.

While SMIC has established itself in mature semiconductor manufacturing processes and serves not only domestic IC design companies but also many Taiwanese IC design firms, it has been actively trying to catch up with foreign giants in advanced manufacturing processes. Additionally, limitations in acquiring equipment like EUV have constrained its progress, making its achievements in the 7-nanometer process a noteworthy accomplishment.

In light of these developments, it has been reported that SMIC has approached Taiwanese partner companies to secure a substantial supply of specific products for an estimated two-year period, likely to be used in their advanced 7-nanometer manufacturing process. SMIC is hoping for proactive cooperation from its supply chain partners to ensure prompt delivery.

(Photo credit: SMIC)

According to a report by Taiwan’s TechNews, Samsung Electronics’ semiconductor foundry division, Samsung Foundry, has been operating at less than 50% utilization rate as of the second quarter due to weak demand for 8-inch wafer foundry services. Industry sources have revealed that Samsung Foundry has already halted operations on 30% of its equipment, but with further inventory reduction expected, there is a possibility of restarting these machines by the end of the year and resuming production in the first quarter of the following year.

Previously, South Korean media outlet The Elec reported that the IT industry’s demand is currently low, leading South Korean wafer foundries to reduce prices for 8-inch wafer services by 10%. As of the second quarter, both Samsung Foundry and other South Korean wafer foundry companies like Key Foundry and SK Hynix System IC, a subsidiary of SK Hynix engaged in foundry operations, have been operating at capacity utilization rates ranging from 40% to 50%.

8-inch wafer services primarily manufacture components such as power management ICs, panel driver ICs, and microcontrollers. Given the uncertain demand for consumer electronics products, Samsung Foundry has decided to halt operations on 30% of its equipment as a cost-saving measure. However, market expectations suggest that the overall manufacturing and semiconductor industries have undergone more than a year and a half of inventory adjustment, and there is hope for inventory replenishment by the end of the year in the supply chains of three major sectors: smartphones, PCs, and consumer electronics.

According to industry sources, Samsung Foundry plans to restart the halted 8-inch wafer equipment by the end of the year and aims to resume full production in the first quarter of the next year. However, the revival of consumer product demand has not yet shown clear signs, and whether the restart will proceed as expected remains to be observed.

(Photo credit: Samsung)

According to a report from Taiwan’s Economic Daily, TSMC’s 3-nanometer technology has attracted another heavyweight client. Following Apple and MediaTek, it is rumored that Qualcomm will also commission TSMC to produce its next-generation 5G flagship chip using the 3-nanometer process. The chip is expected to be unveiled in late October, making Qualcomm the third client for TSMC’s 3-nanometer technology.

In response to these rumors, Qualcomm has not provided any comments, while TSMC has chosen to remain silent. Industry experts speculate that TSMC’s 3-nanometer technology will likely attract additional orders from major players such as NVIDIA and AMD in the future. With various leading-edge fabs continuously seeking TSMC’s services, it appears that TSMC’s 3-nanometer technology remains the top choice for international giants.

Last year, Qualcomm unveiled its annual 5G flagship chip, the “Snapdragon 8 Gen 2,” manufactured using TSMC’s 4-nanometer process. The previous-generation Snapdragon “8 Gen 1” was produced using Samsung’s 4-nanometer process, but it encountered issues related to heat dissipation. Consequently, Qualcomm released an upgraded version, the “Snapdragon 8+ Gen 1,” using TSMC’s 4-nanometer process.

Qualcomm has traditionally adopted a multi-supplier strategy for semiconductor manufacturing. It is rumored in the industry that Qualcomm has privately informed its smartphone brand customers about the upcoming next-generation 5G flagship chip, the “Snapdragon 8 Gen 3,” expected to be announced in late October. This chip will be available in two process versions: TSMC’s 4-nanometer (N4P) and 3-nanometer (N3E).

(Photo credit: TSMC)