Over the past few decades, semiconductor manufacturing technology has evolved from the 10,000nm process in 1971 to the 3nm process in 2022, driven by the need to increase the number of transistors on chips for enhanced computational performance. However, as applications like artificial intelligence (AI) and AIGC rapidly advance, demand for higher core chip performance at the device level is growing.

While process technology improvements may encounter bottlenecks, the need for computing resources continues to rise. This underscores the importance of advanced packaging techniques to boost the number of transistors on chips.

In recent years, “advanced packaging” has gained significant attention. Think of “packaging” as a protective shell for electronic chips, safeguarding them from adverse environmental effects. Chip packaging involves fixation, enhanced heat dissipation, electrical connections, and signal interconnections with the outside world. The term “advanced packaging” primarily focuses on packaging techniques for chips with process nodes below 7nm.

Amid the AI boom, which has driven demand for AI servers and NVIDIA GPU graphics chips, CoWoS (Chip-on-Wafer-on-Substrate) packaging has faced a supply shortage.

But what exactly is CoWoS?

CoWoS is a 2.5D and 3D packaging technology, composed of “CoW” (Chip-on-Wafer) and “WoS” (Wafer-on-Substrate). CoWoS involves stacking chips and then packaging them onto a substrate, creating a 2.5D or 3D configuration. This approach reduces chip space, while also lowering power consumption and costs. The concept is illustrated in the diagram below, where logic chips and High-Bandwidth Memory (HBM) are interconnected on an interposer through tiny metal wires. “Through-Silicon Vias (TSV)” technology links the assembly to the substrate beneath, ultimately connecting to external circuits via solder balls.

The difference between 2.5D and 3D packaging lies in their stacking methods. 2.5D packaging involves horizontal chip stacking on an interposer or through silicon bridges, mainly for combining logic and high-bandwidth memory chips. 3D packaging vertically stacks chips, primarily targeting high-performance logic chips and System-on-Chip (SoC) designs.

When discussing advanced packaging, it’s worth noting that Taiwan Semiconductor Manufacturing Company (TSMC), rather than traditional packaging and testing facilities, is at the forefront. CoW, being a precise part of CoWoS, is predominantly produced by TSMC. This situation has paved the way for TSMC’s comprehensive service offerings, which maintain high yields in both fabrication and packaging processes. Such a setup ensures an unparalleled approach to serving high-end clients in the future.

Applications of CoWoS

The shift towards multiple small chips and memory stacking is becoming an inevitable trend for high-end chips. CoWoS packaging finds application in a wide range of fields, including High-Performance Computing (HPC), AI, data centers, 5G, Internet of Things (IoT), automotive electronics, and more. In various major trends, CoWoS packaging is set to play a vital role.

In the past, chip performance was primarily reliant on semiconductor process improvements. However, with devices approaching physical limits and chip miniaturization becoming increasingly challenging, maintaining small form factors and high chip performance has required improvements not only in advanced processes but also in chip architecture. This has led to a transition from single-layer chips to multi-layer stacking. As a result, advanced packaging has become a key driver in extending Moore’s Law and is leading the charge in the semiconductor industry.

(Photo credit: TSMC)

According to media reports, in response to the booming demand in the artificial intelligence market, TSMC has altered its Kaohsiung factory plan. Originally scheduled for a 28-nanometer mature process, the factory will now be equipped with a 2-nanometer advanced process, with mass production expected to commence in the latter half of 2025. The official announcement of this factory plan is imminent.

During a investor conference held on July 20th, TSMC refrained from making any comments, citing the current quiet period. As reported by “Central News Agency,” Kaohsiung Mayor Chen Chi-mai expressed the city government’s respect for TSMC and pledged full assistance. However, it is worth noting that the 2-nanometer process requires more funding compared to the 28-nanometer process, and TSMC has already informed the Kaohsiung city government, seeking support in terms of water and power supply.

Official data indicates that TSMC’s 2-nanometer process offers a 10% to 15% performance improvement at the same power consumption or a 20% to 30% reduction in power consumption at the same performance level compared to the 3-nanometer process. The primary production base for the 2-nanometer process will be located in Hsinchu’s Baoshan area, with plans to construct four fabs. The trial production is scheduled for 2024, followed by mass production in the latter half of 2025.

(Photo credit: TSMC)

In the continued sluggish consumer electronics market and amidst the booming era of artificial intelligence, semiconductor manufacturers are actively targeting high-performance chips and intensifying the competition over the 2nm process node.

TSMC, Samsung, and the newcomer Rapidus are all actively positioning themselves in the 2nm chip race. Let’s take a look at the progress of these three enterprises.

TSMC: Roadmap for 3nm and 2nm Unveiled

TSMC believes that, at the same power level, the 2nm (N2) chip speed can increase by 15% compared to N3E, or reduce power consumption by 30%, with a density 1.15 times that of its predecessor.

TSMC’s current roadmap for the 3nm “family” includes N3, N3E, N3P, N3X, and N3 AE. N3 is the basic version, N3E is an improved version with further cost optimization, N3P offers enhanced performance, planned for production in the second half of 2024, N3X focuses on high-performance computing devices, and aims for mass production in 2025. N3 AE, designed for the automotive sector, boasts greater reliability and is expected to help customers shorten their product time-to-market by 2 to 3 years.

As for 2nm, TSMC foresees the N2 process to enter mass production in 2025. Media reports from June this year indicate that TSMC is fully committed and has already commenced pre-production work for 2nm chips. In July, the TSMC supply chain revealed that the company has informed equipment suppliers to start delivering 2nm-related machines in the third quarter of next year.

Samsung Electronics: 2nm Mass Production by 2025

In June this year, Samsung announced its latest foundry technology innovations and business strategies.

Embracing the AI era, Samsung’s semiconductor foundry plans to leverage GAA advanced process technology to provide robust support for AI applications. To achieve this, Samsung unveiled detailed plans and performance levels for 2nm process mass production. They aim to realize the application of 2nm process in the mobile sector by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively.

Samsung states that the 2nm process (SF2) offers a 12% performance improvement and 25% power efficiency increase over the 3nm process (SF3), with a 5% reduction in chip area.

Rapidus: 2nm Chip Making Progress

Established in November 2022, Rapidus gained significant attention as eight major Japanese companies, including Sony Group, Toyota Motor, SoftBank, Kioxia, Denso, NTT, NEC and MUFG jointly announced their investment in the company. Just a month after its founding, Rapidus forged a strategic partnership with IBM to jointly develop 2nm chip manufacturing technology.

According to Rapidus’ plans, 2nm chips are set to begin trial production in 2025, with mass production commencing in 2027.

[Update] Intel: Being Ambitious to Start Mass Production Of Its 20A Process in The First Half of 2024

Intel is making a vigorous stride into the semiconductor foundry market, setting its sights on rivals like TSMC and Samsung in the arena of advanced process technologies. Intel’s ambitious road map includes kick-starting mass production of its 20A process in the first half of 2024, followed by an 18A process rollout in 2H24. TrendForce points out, however, Intel has a number of significant hurdles to overcome:

Intel’s longstanding focus on manufacturing CPUs, GPUs, FPGAs, and associated I/O chipsets leaves it short of the specialized processes mastered by other foundries. Therefore, the potential success of Intel’s acquisition of Tower—a move to broaden its product line and market reach—is a matter of crucial importance.

Beyond financial segregation, the division of Intel’s actual manufacturing capabilities poses a pivotal challenge. It remains to be seen whether Intel can emulate the complete separation models like those of AMD/GlobalFoundries or Samsung LSI/Samsung Foundry, staying true to the foundry principle of not competing with clients. Adding complexity to the mix, Intel faces the potential exodus of orders from a key customer—its own design division.

(Photo credit: TSMC)

According to sources cited by Nikkan Kogyo Shimbun, TSMC intends to commence the construction of the second fab in Kikuyo-cho, Kumamoto Prefecture, Japan, in April 2024, with the goal of commencing production before the end of 2026.

It is worth mentioning that news about TSMC’s plan to build its second fab in Japan had already surfaced earlier this year. In January, TSMC’s CEO, CC Wei, revealed that the company was considering establishing a second chip manufacturing facility in Japan. In June, TSMC’s Chairman, Mark Liu, also mentioned during a shareholders’ meeting that the Japanese government expressed a desire for TSMC to continue expanding its investments in Japan, while TSMC was still evaluating the construction of the second fab in the country.

Regarding TSMC’s establishment of a fab in Japan, TrendForce indicated that TSMC has played an instrumental role in fostering the growth of Japan’s semiconductor industry as Japanese fabs are unable to handle manufacturing processes as advanced as 1Xnm. TrendForce posits that TSMC could potentially consider setting up a 7nm production line in Phase 2 of JASM to cater to Japan’s demand for advanced technology. Yet, the ongoing market slowdown necessitates a long-term appraisal before implementing any expansion strategies.

In addition to TSMC, more than 20 new wafer fabs are scheduled for completion in the coming years, despite the industry being in a downturn. According to TrendForce’s statistics report in January this year, there are over 20 planned new wafer fabs worldwide, including 5 in Taiwan, 5 in the United States, 6 in Mainland China, 4 in Europe, and 4 in Japan, South Korea, and Singapore combined.

Furthermore, numerous new wafer fab projects have been announced globally since the beginning of this year. For example, in February, Infineon and Texas Instruments both announced plans to construct new wafer fabs. Infineon plans to invest 5 billion euros to build a 12-inch wafer fab in Germany, while Texas Instruments intends to establish its second 300mm wafer fab in Lehi, Utah, USA. On July 5th, PSMC signed an agreement with SBI of Japan, proposing the establishment of a 12-inch wafer foundry.

Currently, semiconductor resources have become strategic assets. In addition to considering commercial and cost structures, wafer fabs must also account for government subsidy policies, meet customer demands for local production, and maintain supply-demand balance. TrendForce believes that future product diversity and pricing strategies will be key factors for the operation of wafer fabs.

Semiconductor manufacturing leader TSMC held its annual shareholder meeting on June 6, addressing issues including advanced process development, revenue, and capital expenditure. TSMC’s Chairman Mark Liu and President C.C. Wei answered a series of questions. The key points from the industry are summarized as follows:

2023 Capital Expenditure Leaning towards $32 Billion

For TSMC’s Q2 and full-year outlook for this year, the consolidated revenue forecast is between $15.2 and $16 billion, a decrease of 5%-10% from the first quarter. Gross profit margin is expected to range between 52%-54%, and operating profit margin between 39.5%-41.5%. Chairman Mark Liu revealed that this year’s capital expenditure is expected to lean more towards $32 billion.

TSMC’s President C.C. Wei lowered the 2023 growth forecast for the overall semiconductor market (excluding memory), expecting a mid-single digit percentage decrease. The revenue in the wafer manufacturing industry is expected to decrease by a high single digit percentage. At this stage, the overall revenue for 2023 is expected to decrease by a low-to-mid single digit percentage, sliding approximately 1%-6%.

Advanced Process N4P to be Mass Produced this Year

TSMC’s total R&D expenditure for 2022 reached $5.47 billion, which expanded its technical lead and differentiation. The 5-nanometer technology family entered its third year of mass production, contributing 26% to the revenue. The N4 process began mass production in 2022, with plans to introduce the N4P and N4X processes. The N4P process technology R&D is progressing smoothly and is expected to be mass-produced this year. The company’s first high-performance computing (HPC) technology, N4X, will finalize product design for customers this year.

Advanced Packaging Demand Far Exceeds Capacity

Due to the generative AI trend initiated by ChatGPT, the demand for advanced packaging orders for TSMC has increased, forcing an increase in advanced packaging capacity. TSMC also pointed out that the demand for TSMC’s advanced packaging capacity far exceeds the existing capacity, and it is forced to increase production as quickly as possible. Chairman Mark Liu stated that the current investment in R&D focuses on two legs, namely 3D IC (chip stacking) and advanced packaging.

At present, three-quarters of TSMC’s R&D expenditure is used for advanced processes, and one quarter for mature and special processes, with advanced packaging falling under mature and special processes.

(Photo credit: TSMC)