According to a report by Taiwan’s Commercial Times, TSMC is facing a tight supply of advanced packaging capacity, with its Taichung factory ramping up equipment support at a rapid pace. Industry insiders have disclosed that TSMC’s annual production capacity for the backend CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging is only 150,000 to 300,000 units, falling short of customer demand by over 20%.

To address this shortfall, TSMC officially inaugurated its advanced packaging and testing Plant 6 in Zhunan in June. TSMC’s management has also committed to steadily increasing CoWoS production capacity each quarter, and third-party testing facilities are being actively engaged to bridge the gap.

It is worth noting that TSMC’s Longtan factory has traditionally been a key hub for CoWoS and InFO (Integrated Fan-Out) packaging, with a primary focus on InFO production at approximately 100,000 units per month and a smaller portion allocated to CoWoS. Although some of the InFO capacity has been relocated to the Southern Taiwan Science Park, Longtan’s physical space constraints continue to make Zhunan the primary location for CoWoS expansion. TSMC’s Taichung AP5 factory, on the other hand, is prioritizing WoS (Wafer-on-Substrate) expansion, with CoW (Chip-on-Wafer) expansion slated to commence next year. Many equipment suppliers have reportedly received urgent orders related to these expansion efforts.

Analysts estimate that this year’s overall CoWoS production will reach 110,000 units, doubling to 250,000 units next year. However, analysts caution that while TSMC currently dominates the CoWoS production landscape, other players are gradually entering the field. Therefore, it is crucial to monitor whether an oversupply situation may emerge in the mid-term next year.

(Photo credit: TSMC)

On August 29, 2023, Huawei quietly launched its new smartphone, the Huawei Mate 60 Pro, on its official website without the usual fanfare associated with new product releases. Unlike previous events or those held by other brands, Huawei chose to communicate with consumers solely through a letter. What intrigued the market most was the specification of the new device’s System-on-Chip (SoC). Initially, Huawei did not provide any official information about it. However, the release of this new smartphone demonstrates China’s determination to achieve semiconductor self-sufficiency.

Key Insights from TrendForce:

• Overcoming U.S. Sanctions, Huawei Makes a Comeback

In the past, Huawei secured its position as the second-largest player in the global smartphone market by leveraging the differentiating advantage of its in-house developed Kirin SoC chips. However, since May 2019, Huawei has been affected by U.S. sanctions. In September 2020, TSMC, which previously manufactured chips for Huawei, announced the cessation of production. With no supply from TSMC, Huawei’s inventory of 5G chips was depleted by the third quarter of 2022.

Unable to acquire high-end chips, Huawei’s market share in the smartphone industry saw a significant decline. The company could only source 4G chips not subject to U.S. sanctions from Qualcomm or UNISOC. It was believed that U.S. sanctions would severely impact Huawei’s smartphone supply chain and push the company into a dire situation. However, upon analyzing Huawei’s latest release, it is evident that the new smartphone not only features an in-house developed SoC chip by Huawei’s semiconductor subsidiary HiSilicon but also incorporates components and designs from various Chinese manufacturers.

• China’s Semiconductor Self-Sufficiency Continues to Strengthen, Minimal Impact on Taiwanese Supply Chain Expected

China’s pursuit of semiconductor self-sufficiency has become an inevitable outcome of industry development. Although Huawei has not provided detailed specifications for the SoC chip in the Mate 60 Pro, it is speculated that this chip likely uses SMIC’s N+2 process. Due to sanctions, SMIC has been unable to obtain essential EUV equipment. Furthermore, based on the chip’s performance benchmarking, it is comparable to Qualcomm’s flagship Snapdragon 888 chip released in 2021. This suggests that the SoC’s process technology likely falls in the range of 7-14nm, which still lags behind current advanced processes. Nevertheless, this achievement underscores China’s commitment to semiconductor self-sufficiency.

As China gains the ability to independently develop and produce chips, the question arises of whether other Chinese smartphone brands, apart from Huawei, will begin their own chip development efforts. Will this development impact Taiwanese IC design house and foundries that previously held related orders? MediaTek, for instance, primarily supplies chips to brands such as OPPO and vivo. Given that Huawei competes strongly with OPPO and vivo in the smartphone market, it is unlikely that these two brands will entrust their smartphone core SoCs to Huawei’s HiSilicon. Additionally, developing proprietary chips comes with significant costs. Therefore, under these circumstances, it is expected that OPPO and vivo will maintain their partnerships with MediaTek. MediaTek’s chip designs can also utilize TSMC’s advanced processes, giving OPPO and vivo a key competitive advantage against Huawei. Consequently, it is inferred that as long as there is a significant gap between the processes and yields of SMIC and TSMC, Taiwanese foundries will not be significantly affected.

(Photo credit: Huawei)

According to a report by Taiwan’s Commercial Times, the semiconductor market is expected to slow down this year. PSMC Chairman Frank Huang stated that it is estimated that the current wave of semiconductor inventory clearance will not be completed until the end of the first quarter of next year, and the overall market conditions for next year are still not expected to rebound strongly.

When asked about the mature wafer fabs in mainland China aggressively capturing market share this year with low prices, Frank Huang emphasized that this was anticipated. He further stated that PSMC is planning to launch affordable AI chips primarily targeting the consumer market next year, completely differentiating them from Nvidia’s high-priced products. Given the large scale of the consumer market, he expressed optimism regarding future shipment growth.

Huang emphasized that PSMC’s planned AI chips with AI functionality are like miniature computers. Currently, international chip manufacturers offer AI chips with unit prices as high as $200,000, making them impossible for widespread adoption in the consumer market. Therefore, the AI chips PSMC plans to launch next year will have lower prices and will be specifically tailored for the massive consumer market. He gave examples, including affordable AI features being integrated into toys and household appliances. Toys, for instance, will be able to recognize their owners and engage in voice interactions.

Huang mentioned that, because they are targeting affordability and mass appeal, these AI chips will be produced using a 28-nanometer process and are expected to contribute to revenue through formal shipments next year. With a focus on the consumer market, Huang is optimistic about the future shipments and business contributions of these AI chips.

According to a report by Taiwan’s Money DJ, the production schedule for TSMC’s semiconductor foundry in the United States has been delayed until 2025, raising concerns among observers. However, Chairman Mark Liu, in an interview on the 6th, stated that there has been significant progress over the past five months and expressed confidence in the project’s success. Industry sources have indicated that TSMC’s U.S. facility may alter its ramp-up strategy by first establishing a mini-line for trial production, with the expectation of having it in place by the first quarter of 2024.

TSMC’s Fab 21 Phase 1 construction began in April 2021, originally slated for early 2024 production. However, challenges such as a shortage of skilled equipment installation personnel, local union protests, and differences in overseas safety regulations have caused delays in equipment installation. This has compelled TSMC to adjust its plans, and the expected production timeline is now set for 2025, representing a one-year delay.

Industry analysts have noted that the efficiency of equipment entering the facility at TSMC’s U.S. plant in Arizona is only about one-third of that of its Taiwan facilities. Given the current pace of progress, the time required for equipment setup to actual production could be substantial. Therefore, TSMC has decided to change its previous ramp-up strategy and first establish a mini-line with an initial estimated monthly capacity of about 4,000 to 5,000 wafers. This approach aims to ensure some level of production output while mitigating potential contract breach issues arising from delays in production.

(Photo credit: TSMC)

As applications like AIGC, 8K, AR/MR, and others continue to develop, 3D IC stacking and heterogeneous integration of chiplet have become the primary solutions to meet future high-performance computing demands and extend Moore’s Law.

Major companies like TSMC and Intel have been expanding their investments in heterogeneous integration manufacturing and related research and development in recent years. Additionally, leading EDA company Cadence has taken the industry lead by introducing the “Integrity 3D-IC” platform, an integrated solution for design planning, realization, and system analysis simulation tools, marking a significant step towards 3D chip stacking.

Differences between 2.5D and 3D Packaging

The main difference between 2.5D and 3D packaging technologies lies in the stacking method. 2.5D packaging involves stacking chips one by one on an interposer or connecting them through silicon bridges, primarily used for assembling logic processing chips and high-bandwidth memory. On the other hand, 3D packaging is a technology that vertically stacks chips, mainly targeting high-performance logic chips and SoC manufacturing.

CPU and HBM Stacking Demands

With the rapid development of applications like AIGC, AR/VR, and 8K, it is expected that a significant amount of computational demand will arise, particularly driving the need for parallel computing systems capable of processing big data in a short time. To overcome the bandwidth limitations of DDR SDRAM and further enhance parallel computing performance, the industry has been increasingly adopting High-Bandwidth Memory (HBM). This trend has led to a shift from the traditional “CPU + memory (such as DDR4)” architecture to the “Chip + HBM stacking” 2.5D architecture. With continuous growth in computational demand, the future may see the integration of CPU, GPU, or SoC through 3D stacking.

3D Stacking with HBM Prevails, but CPU Stacking Lags Behind

HBM was introduced in 2013 as a 3D stacked architecture for high-performance SDRAM. Over time, the stacking of multiple layers of HBM has become widespread in packaging, while the stacking of CPUs/GPUs has not seen significant progress.

The main reasons for this disparity can be attributed to three factors: 1. Thermal conduction, 2. Thermal stress, and 3. IC design. First, 3D stacking has historically performed poorly in terms of thermal conduction, which is why it is primarily used in memory stacking, as memory operations generate much less heat than logic operations. As a result, the thermal conduction issues faced by current memory stacking products can be largely disregarded.

Second, thermal stress issues arise from the mismatch in coefficients of thermal expansion (CTE) between materials and the introduction of stress from thinning the chips and introducing metal layers. The complex stress distribution in stacked structures has a significant negative impact on product reliability.

Finally, IC design challenges from a lack of EDA tools, as traditional CAD tools are inadequate for handling 3D design rules. Developers must create their own tools to address process requirements, and the complex design of 3D packaging further increases the design, manufacturing, and testing costs.

How EDA Companies Offer Solutions

Cadence, during the LIVE Taiwan 2023 user annual conference, highlighted its years of effort in developing solutions. They have introduced tools like the Clarity 3D solver, Celsius thermal solver, and Sigrity Signal and Power Integrity, which can address thermal conduction and thermal stress simulation issues. When combined with Cadence’s comprehensive EDA tools, these offerings contribute to the growth of the “Integrity 3D-IC” platform, aiding in the development of 3D IC design.

“3D IC” represents a critical design trend in semiconductor development. However, it presents greater challenges and complexity than other projects. In addition to the challenges in Logic IC design, there is a need for analog and multi-physics simulations. Therefore, cross-platform design tools are indispensable. The tools provided by EDA leader Cadence are expected to strengthen the 3D IC design tool platform, reducing the technological barriers for stacking CPU, GPU, or SoC to enhance chip computing performance.

This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC)