According to a report from Nikkei, Japanese memory manufacturer Kioxia has ended production cuts amidst a recovery in the memory market and has secured new bank credit support. The company’s plants in Yokkaichi, Mie Prefecture, and Kitakami, Iwate Prefecture, have restored their production lines to 100% capacity, focusing mainly on NAND flash production.

With improved business conditions, creditor banks have reportedly agreed to refinance a maturing loan of JPY 540 billion (roughly USD 3.43 billion) and have established a new credit line totaling JPY 210 billion (roughly USD 1.33 billion).

Kioxia had previously implemented production cuts in October 2022 due to sluggish demand for smartphone products, reducing output by over 30%. The planned launch of new production lines at the Kitakami plant, originally scheduled for 2023, has been postponed to 2025.

The improved market environment is reflected in Kioxia’s financial report for January to March 2024, where the company achieved a net profit of JPY 10.3 billion, ending six consecutive quarters of losses. Demand for smartphone and personal computer chips has bottomed out and is starting to recover, while orders related to data centers have increased.

As per a previous TrendForce report, Kioxia’s Q1 output was still affected by production cuts from the previous quarter, resulting in a modest 7% QoQ increase in shipments. However, rising NAND Flash prices led to a 26.3% QoQ rise in revenue to $1.82 billion. Kioxia expects to grow Q2 revenue by approximately 20%, supported by increased supply bits and more flexible pricing, which will further expand enterprise SSD shipments.

Per the same report from Nikkei, led by a banking consortium including Sumitomo Mitsui Banking, Mitsubishi UFJ Financial Group, and Mizuho Bank, Kioxia’s improved performance has led to relaxed loan terms and agreement on refinancing along with new credit limits. Additionally, the banks will assist in funding for equipment upgrades.

Read more

• [News] Kioxia Optimistic about NAND Market Sentiment; Price Hike Expected in Q2
• [News] NAND Flash Market Landscape to Change?

(Photo credit: Kioxia)

In 2023, Samsung disclosed plans to launch its advanced three-dimensional (3D) chip packaging technology, which would be able to integrate memory and processors needed for high-performance chips, in much smaller sizes. Now, at the Samsung Foundry Forum in San Jose taken place in June, the tech giant made it public that it would introduce 3D packaging services for HBM within this year, according to the latest report by The Korea Economic Daily.

For now, HBM chips are predominantly packaged with 2.5D technology. Citing industry sources as well as personnel from Samsung, the company’s 3D chip packaging technology is expected to hit the market for HBM4, the sixth generation of the HBM family.

Samsung’s announcement regarding its 3D HBM packaing roadmap has been made after NVIDIA CEO Jensen Huang revealed Rubin at COMPUTEX 2024, the company’s upcoming architecture of its AI platform after Blackwell. The Rubin GPU will reportedly feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, targeting to be released in 2026.

Currently, Samsung’s SAINT (Samsung Advanced Interconnect Technology) platform includes three types of 3D stacking technologies: SAINT S, SAINT L, and SAINT D.

SAINT S involves vertically stacking SRAM on logic chips such as CPUs, while SAINT L involves stacking logic chips on top of other logic chips or application processors (APs). SAINT D, on the other hand, entails vertical stacking of DRAM with logic chips like CPUs and GPUs.

The Korea Economic Daily noted that unlike 2.5D technology, under which HBM chips are horizontally connected with a GPU on a silicon interposer, by stacking HBM chips vertically on top of a GPU, 3D packaging could further accelerate data learning and inference processing, and thus does not require a silicon interposer, a thin substrate that sits between chips to allow them to communicate and work together.

It is also understood that Samsung plans to offer 3D HBM packaging on a turnkey basis, according to the Korea Economic Daily. To achieve this, its advanced packaging team will vertically interconnect HBM chips produced by its memory business division, with GPUs assembled for fabless companies by its foundry unit, the report noted.

Regarding Samsung’s long-time rival, TSMC, the company’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and HBM stacks side by side on one interposer. TSMC also made similar announcement in May, reportedly utilizing 12nm and 5nm process nodes in manufacturing HBM4, according to a report by AnandTech.

Read more

• [News] TSMC Reportedly Prepares Next-generation HBM4 Manufacturing, Utilizing 12nm and 5nm Process
• [News] Samsung Accelerates 3D Packaging with Hybrid Bonding Production Line in Korean Advanced Packaging Hub

(Photo credit: Samsung)

Taiwan’s semiconductor giant, TSMC, faces overwhelming demand for its 3nm technology, with major clients like Apple and NVIDIA fully allocate its production capacity.

According to a report from Commercial Times, orders are expected to be filled through 2026. Reportedly, TSMC is planning to raise its 3nm prices by over 5%, and advanced packaging prices are anticipated to increase by approximately 10% to 20% next year.

The members of TSMC’s 3nm family include N3, N3E, N3P, as well as N3X and N3A. As the existing N3 technology continues to be upgraded, N3E, which began mass production in the fourth quarter of last year, targets applications such as AI accelerators, high-end smartphones, and data centers.

N3P is scheduled for mass production in the second half of this year and is expected to become mainstream for applications in mobile devices, consumer products, base stations, and networking through 2026. N3X and N3A are customized for high-performance computing and automotive clients.

Source: TSMC

Per the industry sources cited by the same report, TSMC’s Zhunan advanced packaging plant (AP6), operational for a year now, has become Taiwan’s largest CoWoS base with the equipment moved into its AP6C plant. In the third quarter, CoWoS monthly production capacity is expected to double from 17,000 to 33,000 wafers.

Industry sources cited by the report further suggests that while AI accelerators do not use the most cutting-edge manufacturing processes, they rely heavily on advanced packaging technology. The ability of global semiconductor companies to secure more advanced packaging capacity from TSMC will determine their market penetration and control.

TSMC’s advanced packaging capacity is scarce, with primary customer NVIDIA having the highest demand, occupying about half of the capacity, followed closely by AMD. Broadcom, Amazon, and Marvell have also expressed strong interest in using advanced packaging processes. With gross margins close to 80%, NVIDIA is said to agree to price increases to secure more advanced packaging capacity, thereby distancing itself from competitors.

Previously, NVIDIA CEO Jensen Huang emphasized that TSMC is not just manufacturing wafers but also handling numerous supply chain issues. He also agreed that the current pricing is too low and would support TSMC’s price increase actions.

The industry sources cited by Commercial Times have indicated that TSMC plans to add CoWoS-related equipment by the third quarter and has requested equipment manufacturers to dispatch more engineers to fully staff its Longtan AP3, Zhunan AP6, and Central Taiwan Science Park AP5 plants.

In addition to Zhunan’s AP6C, the Central Taiwan Science Park plant, which originally only handled the latter stages of oS, will also gradually transition to CoW processes. Meanwhile, the Chiayi site is in the land preparation stage and is expected to progress faster than Tongluo.

Reportedly, industry sources further reveal that the prices for advanced process nodes such as 3nm and 5nm will also be adjusted. Particularly, strong demand for 3nm orders in the second half of the year is expected to drive utilization rates to near full capacity, extending through 2025. The 5nm process is experiencing similar demand dynamics, driven by AI needs.

Read more

• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] NVIDIA CEO Jensen Huang Supports C.C. Wei’s Theory and Backs for TSMC to Increase Price

(Photo credit: TSMC)

One major challenge for China’s IC design industry is the lack of advanced domestic Electronic Design Automation (EDA) tools. Due to US export controls, suppliers like Cadence and Synopsys are unable to provide chip design software to China. Additionally, the absence of domestic EDA tools capable of operating on Chinese-made CPUs adds further pressure.

However, according to a report from TechNews, there are signs of change. Chinese company X-Epic has introduced the first EDA software capable of running on domestically produced processors in China, potentially breaking through existing limitations.

As per a report from Tom’s Hardware, at the Kunpeng Developer Day on April 25, 2024, X-Epic presented the latest developments in China’s domestic chip design software EDA.

This platform is compatible with Huawei’s Kunpeng server processors based on Armv8 architecture and also supports Phytium’s Phytium processors based on SPARCv9 architecture. This represents a significant advancement for China’s semiconductor design industry, enabling domestic chip designers to conduct chip design and simulation using local software only.

X-Epic stated that they provide a comprehensive suite of chip design software EDA tools covering various aspects such as digital chip verification, hardware simulation, system debugging, and cloud-based verification. Extensive adaptation and optimization have already been completed, including adaptation to compilation environments, C++/ASM compilation, cmake compilation scripts, and third-party function libraries. The focus of application lies particularly on Huawei’s Kunpeng platform.

X-Epic has indicated that, through tools like GalaxSim and GalaxFV, X-Epic achieved 2 to 3 times performance enhancements in multiple customer test cases on Huawei’s high-performance Kunpeng server clusters compared to non-optimized software. These enhanced capabilities have notably reduced simulation testing times and improved efficiency in system-level chip simulation verification. However, there is currently no information available regarding test results for Phytium’s Phytium processors.

Overall, this collaboration not only strengthens Huawei’s Kunpeng ecosystem but also provides a comprehensive chip design software EDA solution for China’s domestic semiconductor industry.

Read more

• [News] Huawei’s HarmonyOS Project Ready to Hit the Road with Increasing Participation from Chinese Enterprises
• [Report Highlights] China’s EDA Industry Enters a Period of Consolidation amidst Rapid Growth

(Photo credit: X-Epic)

Following US sanctions in August 2019, Huawei’s internal operating system backup, HarmonyOS, emerged and has been in development for nearly 5 years. Currently, HarmonyOS is widely recognized, and its native version is set to launch on June 21st, marking the cornerstone of Huawei’s ambitious HarmonyOS project.

According to a report from UDN, Huawei is pursuing a dual-track development strategy for HarmonyOS. Internally, it focuses on its “1+8+N” terminal business strategy: “1” refers to smartphones, “8” includes large screens (TVs), tablets, PCs, wearables, car units, and more, while “N” covers a wide range of IoT devices. This approach aims to expand and flourish the HarmonyOS ecosystem.

In essence, HarmonyOS follows two main paths, while the first shares similar market positioning with current market leaders Android and iOS in the consumer sector, primarily focused on Huawei’s own terminal devices, aiming to expand the HarmonyOS ecosystem within the consumer domain.

The second path is OpenHarmony, also known as Open Source HarmonyOS. Reportedly, this initiative involves Huawei’s ecosystem partners leveraging Huawei’s donated OpenHarmony code base to develop their own commercial versions of HarmonyOS. These partners utilize their industry expertise and resources to vertically expand into sectors such as education, finance, transportation, and more. OpenHarmony primarily targets industrial applications.

Vertically, Huawei is reportedly looking to integrate HarmonyOS and OpenHarmony through foundational technology, establishing interoperability and connectivity to create an unified HarmonyOS. This strategic integration is designed to position HarmonyOS as a world-class operating system for the future IoT, aligning with Huawei’s ultimate goal of establishing HarmonyOS as a global IoT OS.

Recently, the unified device interconnection technology standards for OpenHarmony were officially released. Huawei’s Consumer Business Group Chairman, Richard Yu, recently disclosed plans to unify application and service ecosystems across Harmony OS and the commercial versions of OpenHarmony. This initiative aims to enhance consumer and industry experiences by sharing a unified HarmonyOS ecosystem that includes programming languages, compilers, and tools, thereby constructing a comprehensive smart terminal operating system.

Huawei is also said to be advancing another significant vertical initiative: the native HarmonyOS. Currently, Huawei has successfully developed the entire stack of HarmonyOS as an independent Chinese-made operating system, contrasting with the majority of global operating systems such as Android and iOS, which are based on the Linux or Unix kernel.

Huawei’s recent strides not only shape the future of HarmonyOS and OpenHarmony but also bolster Huawei’s autonomy and control. These developments are crucial for China’s tech enterprises, providing resilience against potential US sanctions. Whether in consumer or industrial sectors, the Mega HarmonyOS can be activated promptly, underscoring why numerous Chinese companies are joining the HarmonyOS ecosystem.