According to a report from Nikkei News, US chip giant Intel will join forces with 14 Japanese companies to develop automation technology for “backend” semiconductor processes such as packaging. The aim is said to achieve automation by 2028, highlighting efforts by both the US and Japan to collaborate and reduce geopolitical risks in the semiconductor supply chain.

Intel’s collaborating partners include Japanese firms such as Omron, Yamaha Motor, Resonac, and Shin-Etsu Polymer, a subsidiary of Shin-Etsu Chemical Industry. The alliance, led by Intel Japan’s Managing Director Kunimasa Suzuki, plans to invest hundreds of billions of Japanese Yen in research and development, aiming to demonstrate technological achievements before 2028.

In the semiconductor field, as “frontend” process technologies such as circuit formation approach physical limits, the focus of technological competition is gradually shifting to “backend” processes such as chip stacking to enhance performance.

Most semiconductor backend processes are currently carried out through manual labor, leading to the concentration of factories in China and Southeast Asian countries with abundant labor force. However, to establish plants in countries like the US and Japan, where labor costs are higher, industry players consider automation technology as a crucial prerequisite.

Led by Intel, the alliance plans to establish backend production lines in Japan in the coming years, aiming for full automation. They also intend to standardize backend technologies to manage and control manufacturing, inspection, and equipment processing procedures under a single system.

According to data from the Japanese Ministry of Economy, Trade and Industry, Japanese companies currently hold a 30% share of the global semiconductor production equipment market and dominate approximately half of the semiconductor materials market.

It is widely expected that the Japanese Ministry of Economy, Trade and Industry will allocate hundreds of billions of Japanese Yen in subsidies for this project. The Japanese government has allocated approximately JPY 4 trillion (around USD 26 billion) from fiscal year 2021 to 2023 to support key industries contributing to economic security.

In April of this year, Japan approved a subsidy of JPY 53.5 billion to Rapidus to assist in backend technology development. Additionally, there are considerations to offer incentives to attract global backend capacity providers to establish operations in Japan.

Japanese and American policymakers are attempting to keep most of the chip manufacturing processes within their own territories, aiming to reduce risks in critical supply chains.

TrendForce has previously reported that Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

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• [News] Overseas Expansion of Testing and Packaging Facilities – Japan, Malaysia, and Singapore Emerge as Top Choices
• [News] Rapidus Focuses on Small Clients, Diversifies into Japan to Mitigate US Geopolitical Risks

(Photo credit: Intel)

According to TrendForce’s latest memory spot price trend report, due to a significant increase in DRAM module contract prices, some buyers are turning to spot inquiries, leading to partial transactions at lower prices. Meanwhile, NAND Flash prices have shown loosening in spot prices as certain module manufacturers adopt a more cautious approach towards future wafer price trends, reducing their inventory buildup. Details are as follows:

DRAM Spot Price:

Spot prices of DRAM chips have yet to rebound, and the overall chip transaction volume has been limited due to the tepid demand situation. Regarding DRAM modules, some spot transactions have been arranged in the lower price range as a few buyers experiencing significant increases in the contract market have sought quotes in the spot market. Currently, the May Day holiday is taking place in China, so the spot market has been rather quiet in recent days. Looking ahead, an important market indicator is whether inventory-related preparations for the 618 Sales Event will lead to a notable demand increase. The average spot price of the mainstream chips (i.e., DDR4 1Gx8 2666MT/s) has not changed from last week and is holding steady at US$1.949.

NAND Flash Spot Price:

A number of module houses, who are reserved towards future wafer price trends, are no longer building significant inventory in order to achieve austerity to maintain their cash required for operations. This has led to a loosening in spot prices. Suppliers are attempting to avoid another predicament of excessive provision by controlling product availability, though such action has proven to be quite restricted pertaining to the increase of packaged die prices. Spot prices of 512Gb TLC wafers have dropped by 0.99% this week, arriving at US$3.708.

SK Hynix has been exploring the potential of manufacturing 3D NAND at ultra-low temperatures, which may enable the South Korean memory giant to produce its new-generation product with over 400 layers, South Korea’s media outlet TheElec revealed.

According to the report, instead of testing in its own wafer fabs, SK Hynix has sent test wafers to Tokyo Electron (TEL) to test the performance of the latter’s latest cryogenic etching tool. Unlike existing ones, which usually operate at 0~30°C, the Japanese fab equipment maker’s new etching equipment is capable of performing high-speed etching at -70°C.

According to a press release by TEL, its latest memory channel hole etch technology enables a 10-µm-deep etch with a high aspect ratio in just 33 minutes. It can also reduce the global warming potential by 84% compared with previous technologies.

Industry sources cited by the report indicated that SK Hynix plans to utilize a triple-stack structure for 321-layer NAND. However, when it comes to etching in deep channel holes, achieving uniformity is a major challenge. As a result, companies usually adopt double or even triple-stack structures for 3D NAND manufacturing due to the considerable difficulty in etching vertical holes.

With the help of TEL’s new etching equipment, it may be possible in the future to manufacture 3D NAND with over 400 layers, even in structures with fewer stacked layers, allowing memory manufacturers to reduce costs thanks to simplified processes. SK Hynix aims to produce 3D NAND products with over 400 layers, and depending on their performance, these NAND chips may adopt single or double-stack structures.

(Photo credit: SK hynix)

With the skyrocketing demand for AI, cloud service providers (CSPs) are hastening the development of in-house chips. Apple, making a surprising move, is actively developing a data center-grade chip codenamed “Project ACDC,” signaling its foray into the realm of AI accelerators for servers.

As per a report from global media The Wall Street Journal, Apple is developing an AI accelerator chip for data center servers under the project name “Project ACDC.” Sources familiar with the matter revealed that Apple is closely collaborating with TSMC, but the timing of the new chip’s release remains uncertain.

Industry sources cited by the same report from Commercial Times disclosed that Apple’s AI accelerator chip will be developed using TSMC’s 3-nanometer process. Servers equipped with this chip are expected to debut next year, further enhancing the performance of its data centers and future cloud-based AI tools.

Industry sources cited in Commercial Times‘ report reveal that cloud service providers (CSPs) frequently choose TSMC’s 5 and 7-nanometer processes for their in-house chip development, capitalizing on TSMC’s mature advanced processes to enhance profit margins. Additionally, the same report also highlights that major industry players including Microsoft, AWS, Google, Meta, and Apple rely on TSMC’s advanced processes and packaging, which significantly contributes to the company’s performance.

Apple has consistently been an early adopter of TSMC’s most advanced processes, relying on their stability and technological leadership. Apple’s adoption of the 3-nanometer process and CoWoS advanced packaging next year is deemed the most reasonable solution, which will also help boost TSMC’s 3-nanometer production capacity utilization.

Generative AI models are rapidly evolving, enabling businesses and developers to address complex problems and discover new opportunities. However, large-scale models with billions or even trillions of parameters pose more stringent requirements for training, tuning, and inference.

Per Commercial Times citing industry sources, it has noted that Apple’s entry into the in-house chip arena comes as no surprise, given that giants like Google and Microsoft have long been deploying in-house chips and have successively launched iterative products.

In April, Google unveiled its next-generation AI accelerator, TPU v5p, aimed at accelerating cloud-based tasks and enhancing the efficiency of online services such as search, YouTube, Gmail, Google Maps, and Google Play Store. It also aims to improve execution efficiency by integrating cloud computing with Android devices, thereby enhancing user experience.

At the end of last year, AWS introduced two in-house chips, Graviton4 and Trainium2, to strengthen energy efficiency and computational performance to meet various innovative applications of generative AI.

Microsoft also introduced the Maia chip, designed for processing OpenAI models, Bing, GitHub Copilot, ChatGPT, and other AI services.

Meta, on the other hand, completed its second-generation in-house chip, MTIA, designed for tasks related to AI recommendation systems, such as content ranking and recommendations on Facebook and Instagram.

Read more

• [News] Breaking Away from NVIDIA Dependency, Microsoft Reportedly Developing In-House AI Server High-Speed Network Card
• [Insights] AI Market: A Battleground for Tech Giants as Six Major Companies Develop AI Chips

(Photo credit: Apple)

According to a report from Economic Daily News citing The Wallstreet Journal, Apple is rumored to be developing its own AI chips tailored for data centers, which could potentially give the world’s top smartphone seller a crucial advantage in the AI arms race. The report, quoting sources familiar with the matter, stated that Apple has been working closely with its chip manufacturing partner TSMC to design and produce these chips in the primary stage. However, it is still unclear whether the final version has been produced yet.

It is suggested that Apple’s server chips may focus on executing AI models, particularly in AI inference, rather than AI training, where Nvidia’s chips currently dominate.

Over the past decade, Apple has gradually become a major player in chip design for products like iPhone, iPad, Apple Watch, and Mac. The latest project involving Apple chips for data center servers, internally named “Project ACDC” (short for Apple Chips in Data Center), will integrate Apple’s IC design capabilities into the operation of clients’ servers, sources said.

The project has been in operation for several years, though the timetable for launching this server chip remains unclear. Apple is expected to unveil more new AI products and AI-related updates at its Worldwide Developers Conference (WWDC) in June.

An Apple spokesperson declined to comment on the reported developments.

According to reports from Wccftech on April 23rd, Apple is said to be working on a self-developed AI server processor using TSMC’s 3-nanometer process, with plans for mass production expected in the second half of 2025.