Per a report from TechNews, during Intel’s earnings call last week, CEO Pat Gelsinger stated that the supply of Core Ultra processors in the second quarter is limited due to insufficient wafer-level assembly capacity.

Gelsinger mentioned in the meeting that with the increasing demand for AI PCs and customers continually adding processor orders to Intel due to Windows update cycles, Intel’s AI PC CPU shipments for 2024 are expected to surpass the originally set target of 40 million units. In response, Intel is actively ramping up production to meet customer demand, with the current supply bottleneck primarily concentrated in the backend wafer-level assembly.

Wafer-level assembly is a technology where packaging is done on wafers before they are cut into chips, widely utilized in processors like Meteor Lake and future Core Ultra processors. However, in the face of overwhelming demand, this production bottleneck has led Intel’s Consumer Computing Division to anticipate second-quarter revenue to be roughly equivalent to that of the first quarter, around USD 7.5 billion.

To address this issue, Intel is actively enhancing its wafer-level assembly capacity to meet the growing orders. It is expected that the current tight situation will be alleviated in the second half of 2024, facilitating further revenue growth for the Consumer Computing Division.

As per previous report by Economic Daily News, Intel has advanced packaging capacity in Oregon and New Mexico in the United States and is actively expanding its advanced packaging capabilities in its new facility in Penang. It is noteworthy that Intel once stated its intention to offer customers the option to only use its advanced packaging solutions, expected to provide customers with greater production flexibility.

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(Photo credit: Intel)

Japan is reportedly planning to expand export restrictions on four technologies related to semiconductors or quantum computing, as per a report from Bloomberg. This move is said to represent the latest initiative in global efforts to control the transfer of strategic technologies.

The same report indicates that Japan’s new measures will affect the export of scanning electron microscopes used for analyzing nano-particle images, as well as the technology for improving semiconductor design known as Fully Depleted Silicon on Insulator (FD-SOI) technology. Japan will also require licenses for the low-temperature CMOS circuits used in quantum computers, as well as for the outputs of quantum computers themselves. These restrictions apply to Japan’s most significant trading partners, including South Korea, Singapore, and Taiwan.

The Japanese Ministry of Economy, Trade, and Industry recently stated that the purpose of this plan is to better regulate the export of components for military purposes and to align with similar initiatives around the world. Reportedly, the Ministry emphasized that after public consultations ending on May 25th, while this plan is expected to take effect as early as July.

In fact, in 2023, Japan expanded export restrictions on 23 types of cutting-edge semiconductor manufacturing technologies. The implementation of these controls followed after the United States restricted China’s access to crucial semiconductor fabrication technologies. At that time, reportedly, Washington officials lobbied international partners such as Japan and the Netherlands to impose trade sanctions on China, aligning with the U.S. view of China as a geopolitical and potential military competitor.

Export controls chief Alan Estevez, as reported by Reuters during an annual conference, emphasized the importance of discussions with allies regarding key component servicing. He mentioned ongoing efforts to assess which components require servicing, hinting at the US’s reluctance to impose restrictions on non-core components that Chinese firms can repair independently.

Since then, the US has reportedly been urging allies such as the Netherlands, Germany, South Korea, and Japan, urging them to further tighten restrictions on China’s access to advanced chip technology.

According to a previous report from Nikkei News, the U.S. government initiated semiconductor export controls in various fields, including manufacturing equipment, in October 2022. This decision stems from the belief that semiconductors, which play a crucial role in new-generation technologies such as AI and autonomous driving, are strategic commodities directly related to national power.

Consequently, the U.S. government requested further cooperation from Japan and the Netherlands, leading to both countries strengthening their controls in 2023. However, despite these measures, exports of related products, excluding those under control, to China are sharply increasing. Therefore, the U.S. government believes it is necessary to urge Japan and the Netherlands, which have advantages in semiconductor manufacturing equipment, to take further actions.

Currently, manufacturing equipment required for advanced semiconductors with range of 10 to 14 nanometers and below are subject to export control restrictions. The United States is pushing to expand regulations to include certain equipment for what are known as general-purpose semiconductors.

This request is believed to potentially encompass exposure equipment used on silicon wafers, as well as etching equipment for three-dimensional stacking in. Among Japanese companies, Nikon and Tokyo Electron possess advanced capabilities in this field.

The same report from Nikkei News further notes that the restrictions also extend to materials related to Shin-Etsu Chemical Industries, such as photosensitive materials, and demand restrictions on exports to China. Additionally, the United States is preparing to request that the Netherlands cease providing maintenance and services for manufacturing equipment sold to China before the 2023 regulations. The strengthened control will also have a certain impact on allied countries.

Currently, Dutch company ASML is believed to still be providing such services to Chinese buyers. Per ASML’s financial report, during Q1, machine revenue from the Chinese market increased significantly from the previous quarter’s 39% to 49%.

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(Photo credit: ASML)

As the global semiconductor landscape undergoes restructuring, major packaging and testing companies are actively establishing overseas advanced packaging capacities. According to a report from Commercial Times, semiconductor industry sources have indicated that, in terms of the clustering effect within the semiconductor industry, the primary targets currently include Japan, Malaysia, and Singapore.

Industry sources cited by the same report have pointed out that the global top ten packaging and testing companies are dominated by Taiwan, China, and the United States. Taiwan holds the lead with five industry giants including ASE Group, Powertech Technology, King Yuan Electronics CO. (KYEC), Chipbond Technology, ChipMos and Sigurd.

China boasts four key players such as Jiangsu Changjiang Electronics Technology Co., Tongfu Microelectronics, and Huatian Technology Co. Meanwhile, the United States is represented by Amkor, the world’s second-largest in scale. Japan’s pursuit of rebuilding the packaging and testing industry through a foundry model and seeking support from Taiwanese companies can be seen as a logical progression.

Given that nine out of the top ten packaging and testing companies are located in the Asia-Pacific region, the strategic positioning in Asia is particularly notable, with Japan, Malaysia, and Singapore all striving to make their mark.

Industry sources cited by the same report point out that Malaysia has been developing its semiconductor industry for decades, with Penang being a prominent semiconductor hub. Not only does Penang boast technological advantages, but it is also dubbed the “Silicon Valley of the East.”

As companies like TSMC, Samsung, and Intel expand their fabs to locations such as the United States and Europe, the downstream semiconductor testing and packaging activities are gradually forming clusters in Malaysia. This includes ASE Group’s significant investment in building a new testing and packaging facility in Penang, scheduled for completion in 2025.

Intel is also planning to establish advanced packaging facilities in both Penang and Kedah. Additionally, Texas Instruments from the United States has announced plans to build semiconductor testing and packaging facilities in Kuala Lumpur and Malacca.

While Malaysia’s testing and packaging sector has become a hub, industry sources cited by the report point out that despite many countries aggressively building their semiconductor industry chains, Japan is seen as the country, outside of Taiwan, with the most comprehensive semiconductor supply chain in the future, due to factors such as cultural traits, industrial development experience, geographical proximity to Taiwan, and long-standing close cooperation.

TrendForce has previously reported that Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

With Japan rapidly catching up in development, it becomes necessary for companies like ASE Group to strengthen their presence in Japan. The sources cited by the report are optimistic that Taiwanese-owned testing and packaging facilities may follow suit.

Recently, Powertech Technology Inc., Taiwan’s testing and packaging company, expressed openness to exploring opportunities in Japan, including seeking subsidies from the Japanese government, following the model set by TSMC.

Singapore is also actively strengthening its semiconductor industry chain. Per official Singaporean data, out of the 15 world-class chip design companies, 9 have established bases in Singapore. Additionally, there are 14 semiconductor fabs and 20 semiconductor assembly and testing facilities.

Coupled with the nearby established backend testing clusters in Malaysia, if Singapore constructs a more complete industry chain, it is poised to attract even more world-class testing and packaging companies to establish their presence there.

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Following TSMC’s announcement of investing USD 20 billion to build two plants in Kumamoto, Japan, industry sources cited by a report from Commercial Times has indicated that the major global semiconductor assembly and testing provider, ASE Group, is in discussions with the Japanese government to finalize subsidies and investment details.

Reportedly, ASE plans to invest nearly NTD 10 billion (roughly USD 306.3 million) to construct its first advanced packaging plant in Kumamoto, becoming the second Taiwanese semiconductor giant to set foot in the region.

Regarding the establishment of a plant in Kumamoto, ASE Group stated that it does not comment on market rumors.

During its earnings call last week, ASE Group announced a capital expenditure increase to expand related capacities due to the upward adjustment in advanced packaging projects. This year’s capital expenditure, originally estimated at around USD 2.1 billion with a year-on-year increase of over 40%, has been raised to a potential 50% increase (up to USD 2.25 billion), potentially reaching a historic high.

The semiconductor industry is witnessing a great era of global competition with various countries pouring money into subsidies. Recently, there have been rumors of the Japanese government actively reaching out to Taiwanese semiconductor companies and offering substantial subsidies, aiming to build a complete semiconductor industry chain covering upstream, midstream, and downstream sectors.

Apart from TSMC’s decision to establish two advanced semiconductor plants in Kumamoto, Intel is also considering establishing an advanced packaging research institution in Japan, and Samsung is planning to set up advanced packaging research facilities in Yokohama.

Industry sources cited by the same report point out that these signs have indicated that after mastering wafer manufacturing technology, the next phase for Japan is to enhance the establishment of the packaging industry.

Industry rumors have recently circulated that the Japanese government has been in discussions with senior executives from ASE Group for some time, and the relevant subsidy and investment details are generally agreed upon. The location for the new facility is expected to be in Kumamoto, near TSMC’s upcoming plant. As per the same report citing sources, there is a chance that ASE’s Kumamoto facility, like TSMC’s second plant in Kumamoto, will be planned to start production before the end of 2027.

In fact, as early as 2004, ASE Group acquired full ownership of an IC packaging and testing facility in Yamagata Prefecture, Japan, from NEC for USD 80 million. However, over the past two decades, Japan’s influence in the global semiconductor sector has waned, and ASE’s acquisition of the NEC facility has not made significant operational contributions.

ASE Group’s global footprint currently includes high-end product bases in Taiwan, as well as its packaging and testing capacities in China, Japan, Malaysia, South Korea, and Singapore.

ASE is continuing its expansion efforts in Taiwan, including Kaohsiung, Zhongli, and Tanzi. Evenmore, on February 22nd, ASE Group and semiconductor giant Infineon Technologies jointly announced the finalization of an agreement. ASE Group will invest EUR 62.589 million to acquire Infineon’s backend packaging facilities located in Cavite, Philippines, and Cheonan, South Korea.

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TSMC unveiled its angstrom-class A16 advanced process during the Company’s 2024 North America Technology Symposium on April 25, set to be mass-produced in 2026. Not only is this earlier than competitors like Intel’s 14A and Samsung’s SF14, both slated for 2027 production, but TSMC also emphasized that the A16 does not require the use of High-NA EUV, making it more cost-competitive.

TSMC’s A16 to Lead Competitors in Production Time and Cost

According to TSMC, the A16 advanced process, combining Super PowerRail and nanosheet transistors, is set for mass production in 2026. Super PowerRail relocates power networks to the backside of wafers, freeing up more space on the frontside for signal networks, enhancing logic density and performance. This is ideal for High-Performance Computing (HPC) products with complex signal routing and dense power networks.

Compared to TSMC’s N2P process, the A16 offers an 8% to 10% speed increase at the same Vdd (operating voltage), a 15% to 20% reduction in power consumption at the same speed, and a density increase of up to 1.1 times, supporting data center products.

Photo credit: TSMC

Additionally, as AI chip companies are eager to optimize designs to leverage the full potential of TSMC’s processes, as per a report from Reuters, TSMC doesn’t believe that ASML’s latest High-NA EUV is necessary for producing A16 process chips.

Furthermore, TSMC showcased the Super Power Rail architecture, slated to be operational in 2026, which delivers power from the backside of the chip, aiding in the accelerated operation of AI chips.

Intel 14A Extends ‘5 Nodes in 4 Years’ Strategy

In February, Intel unveiled its 14A process, which would be after its “5 Nodes in 4 Years” strategy. After integrating High-NA EUV production, Intel 14A is expected to improve energy efficiency by 15% and increase transistor density by 20% compared to Intel 18A.

The enhanced version, Intel 14A-E, will further boost energy efficiency by 5% based on Intel 14A. According to the plan, Intel 14A is set for mass production as early as 2026, while Intel 14A-E is slated for 2027.

Photo credit: Intel

Intel recently announced the completion of the industry’s first commercial High-NA EUV lithography tool assembly. The ASML TWINSCAN EXE:5000 High-NA EUV lithography tool is undergoing multiple calibrations and is scheduled to be operational in 2027 for Intel’s 14A process.

Intel emphasizes that when the High-NA EUV lithography tool is combined with its other leading process technologies, it reduces print size by 1.7 times compared to existing EUV machines. This reduction in 2D dimensions increases density by 2.9 times, aiding Intel in advancing its process roadmap.

Samsung SF1.4 Enhances Performance and Power Efficiency with Nanosheet Addition

Photo credit: Samsung

Compared to TSMC and Intel, Samsung’s progress in the angstrom era seems somewhat lagging. Two years ago at the Samsung Foundry Forum 2022, Samsung unveiled its advanced process roadmap, with the angstrom-level SF1.4 (1.4 nanometers) set for mass production in 2027.

Last October, Samsung’s Vice President of Foundry, Jeong Gi-Tae, reportedly told the Korean media outlet The Elec that Samsung has announced its upcoming SF1.4 (1.4-nanometer class) process technology, which would increase the number of nanosheets from 3 to 4. This move is expected to bring significant benefits in chip performance and power consumption

Samsung announced the mass production of SF3E (3nm GAA) in June 2022, introducing a new Gate-All-Around (GAA) architecture. This year, they unveiled the second-generation 3nm process, SF3 (3nm GAP), utilizing the second-generation Multi-Bridge Channel Field Effect Transistor (MBCFET) to optimize performance based on the SF3E foundation.

Additionally, they introduced the performance-enhanced SF3P (3GAP+), suitable for manufacturing high-performance chips. By 2025, Samsung plans to scale up production of the SF2 (2nm) process, followed by mass production of the SF1.4 (1.4nm) process in 2027.

Reportedly, Samsung aims to increase the number of nanosheets per transistor to enhance drive current and improve performance. More nanosheets allow higher current to pass through the transistor, enhancing switching capability and operational speed.

Moreover, more nanosheets offer better control over current, helping to reduce leakage and lower power consumption. Improving current control means transistors generate less heat.

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