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Rumors have been circulating regarding Samsung’s 3nm yield recently. The latest market speculation on June 25th alleged that Samsung’s foundry plant encountered a defect impacting 2,500 lots in the 3nm second-generation process, reportedly leading to a loss of 1 trillion won (USD 720 million), according to the latest report by the Chosun Daily.
On June 26th, the semiconductor giant denied the rumors of a major defect in the production of semiconductor wafers at its foundry division in South Korea. Market speculations emerged earlier, suggesting that all the affected wafers, which equal to 2,500 lots, had to be discarded, the report noted. The volume corresponds to roughly 65,000 12-inch equivalent wafers per month.
According to the Chosun Daily, Samsung claimed that the rumor of “discarding them (the affected wafers) all” circulating in the stock market are unfounded. The current status of the products from the affected production line is still under evaluation, the report said.
Citing industry insiders familiar with the matter, the Chosun Daily noted that the reported figures might be exaggerated, pointing out that Samsung’s 3nm production capacity is less than 60,000 wafers per month. Furthermore, there are numerous inspection processes in place throughout the production line, indicating that such a large-scale defect may be improbable.
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(Photo credit: Samsung)
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On June 26, American memory manufacturer Micron announced its financial results for the third quarter of the 2024 fiscal year (ending May 30, 2024) after the market closed: revenue increased by 82% year-over-year (17% quarter-over-quarter) to $6.811 billion; Non-GAAP diluted earnings per share (EPS) were reported at $0.62, better than the $0.42 of the second quarter of the 2024 fiscal year and the diluted loss per share of $1.43 in the third quarter of the 2023 fiscal year.
Micron further estimates that for the fourth quarter of the 2024 fiscal year, revenue and Non-GAAP diluted EPS will be $7.6 billion (plus or minus $200 million) and $1.08 (plus or minus $0.08), respectively.
Per a Bloomberg report on June 26th, some sources expect Micron’s fourth-quarter revenue to exceed USD 8 billion.
Micron CEO Sanjay Mehrotra stated in a press release that the improving market conditions and strong price and cost execution drove the financial outperformance. Reportedly, Micron’s total fiscal Q3 revenue was USD 6.8 billion, up 17% sequentially and up 82% year over year.
Mehrotra also noted that Micron’s market share for high-margin AI-related product categories such as HBM (high-bandwidth memory), high-capacity DIMMs and data center SSDs continue to rise. Meanwhile, Micron is also gaining share in data center SSD, reaching new revenue and market share records in this important product category.
Mehrotra stated during the earnings call that strong AI-driven demand for data center products has led to tight capacity for advanced processes. Therefore, despite steady recent demand for personal computers (PCs) and smartphones, Micron expects prices to continue rising throughout 2024 (January to December).
Micron CEO Sanjay Mehrotra further addressed, “In the data center, rapidly growing AI demand enabled us to grow our revenue by over 50% on a sequential basis.” He then pointed out, “…we can deliver a substantial revenue record in fiscal 2025, with significantly improved profitability underpinned by our ongoing portfolio shift to higher-margin products.”
Looking ahead to 2025, the growing demand for AI PCs, AI smartphones, and data center AI creates a favorable environment, giving Micron confidence in achieving substantial revenue records in the 2025 fiscal year. This is expected to significantly boost profitability as the product mix continues to shift towards higher-margin products.
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(Photo credit: Micron)
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After ending production cuts amidst a recovery in the memory industry, Kioxia disclosed its plans on the 3D NAND roadmap last week. According to reports from PC Watch and Blocks & Files, Kioxia stated that achieving a 1,000-layer level by 2027 would be possible.
According to the reports, the number of 3D NAND layers has generally increased from 24 in 2014 to 238 in 2022, representing a tenfold rise over eight years. Kioxia stated that achieving a 1,000-layer level by 2027 would be possible at a rate of increase of 1.33 times per year.
The Japanese memory chipmaker seems to be more ambitious than Samsung regarding the battle of layers. In May, Samsung revealed its target to release advanced NAND chips with over 1000 layers by 2030. According to Wccftech, the South Korean memory giant plans to apply new ferroelectric materials on the manufacturing of NAND to achieve this goal.
According to the latest analysis from TrendForce, Kioxia has benefited from the recovery of the memory industry, recently receiving subsidies from the Japanese government and additional financing from a consortium of banks. Furthermore, the company plans to launch an IPO by the end of the year. These measures have provided Kioxia with ample financial resources to pursue technological advancements and cost optimization.
TrendForce further notes that Kioxia has ambitious plans to achieve 1000-layer technology by 2027, which is the highest number of layers announced by any manufacturer so far. However, to reach the milestone, it will be necessary to transition from TLC (3 bits per cell) to QLC (4 bits per cell), and possibly even to PLC (5 bits per cell). The technical challenges involved are significant, and whether Kioxia can achieve this market milestone by 2027 remains to be seen.
The Battle of Layers between Memory Giants
Kioxia and its partner Western Digital showcased their 218-layer technology in 2023 following the 162-layer milestone. Its current announcement to achieve the 1000-layer technology by 2027 would be a huge leap from that.
The battle of layers between memory giants has been intensifying as other memory heavyweights had already surpassed the 200-layer milestone. Earlier in April, Samsung confirmed that it has begun mass production for its one-terabit (Tb) triple-level cell (TLC) 9th-generation vertical NAND (V-NAND), with the number of layers reaching 290, according an earlier report by The Korea Economic Daily. For now, the company aims to stack V-NAND to over 1000 layers by 2030.
SK Hynix unveiled the world’s highest-layer 321-layer NAND flash memory samples in August 2023, claiming to have become the industry’s first company developing NAND flash memory with over 300 layers, with plans for mass production by 2025. Micron has also started to mass produce its 232-layer QLC NANDs in 2024.
Uncertainties behind Kioxia’s Optimism
However, to Kioxia, there are more challenges to overcome, as technological obstacles and Western Digital’s stance add uncertainties to its ambition. According to the report from Blocks & Files, increasing density in a 3D NAND die involves more than just adding layers, as each layer’s edge must be exposed for memory cell electrical connectivity. This results in a staircase-like profile, and as the number of layers grows, the die area needed for the staircase expands as well.
Therefore, to increase density, it is necessary to shrink the cell size both vertically and laterally, and to raise the bit level as well. All these scaling factors, including layer counts, vertical cell size reduction, lateral cell size reduction, and cell bit level increases, present their own technological challenges.
Moreover, according to Blocks & Files, WD has concerns regarding the manufacturing capital costs and the return on investment from selling chips and SSDs made with the fabricated NAND dies.
Citing Western Digital EVP Robert Soderbery in June, the report noted that in the 3D era, NAND manufacturing requires higher capital intensity but offers a lower cost reduction as bit density increases. The company even described the situation as the “end of the layers race,” indicating that there would be a slowdown in the rate of NAND layer count increases to optimize capital deployment.
How long would the battle of layers continue, and how far would it go? Technological breakthroughs as well as the willingness to endure higher capital intensity while the cost reduction being relatively limited may be key.
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(Photo credit: Kioxia)
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AI applications is driving the memory market forward, with HBM (High Bandwidth Memory) undoubtedly being a sought-after product of the industry, attracting increased capital expenditure and production expansion from memory manufacturers. At the meantime, a new force in the memory market has quietly emerged: GDDR7 is expected to drive the memory market steadily forward as HBM amid the AI wave.
GDDR7 and HBM both belong to the category of graphics DRAM with high bandwidth and high-speed data transmission capabilities, providing strong support for AI computing. However, GDDR7 and HBM differ slightly in terms of technology, application scenarios, and performance.
GDDR7 is the latest technology in the GDDR family primarily used to enhance the available bandwidth and memory capacity of GPU. In March 2024, JEDEC, the Solid State Technology Association, officially released the JESD239 GDDR7 standard, which significantly increases bandwidth, eventually reaching 192GB/s per equipment.
It can be calculated that the memory speed is 48Gbps, double that of GDDR6X, the number of independent channels double from 2 in GDDR6 to 4 in GDDR7, and it supports densities ranging from 16-32 Gbit, including support for 2-channel mode to double system capacity.
Additionally, JESD239 GDDR7 is the first JEDEC-standard DRAM to use a Pulse Amplitude Modulation (PAM) interface for high-frequency operation. Its PAM3 interface improves the signal-to-noise ratio (SNR) in high-frequency operations while improving energy efficiency.
GDDR7 is mainly applied in graphics processing, gaming, computing, networking, and AI, particularly in gaming, where its high bandwidth and high-speed data transmission capabilities can significantly improve frame smoothness and loading speed, enabling a better experience for game players. In the field of AI, GDDR7 boasts great potential, capable of supporting rapid data processing and computation for large AI models, thus speeding up model training and inference.
Michael Litt, chairman of the JEDEC GDDR Task Group, has stated that GDDR7 is the first to focus not only on bandwidth but also on integrating the latest data integrity features to meet the market demands for RAS (Reliability, Availability, and Serviceability). These features allow GDDR devices to better serve existing markets like cloud gaming and computing, and expand its presence to AI sector.
Based on memory stacking technology, HBM connects layers through Through-Silicon Via (TSV), and features high capacity, high bandwidth, low latency, and low power consumption. Its strength lies in breaking the memory bandwidth and power consumption bottleneck. Currently, HBM is mainly used in AI server and supercomputer applications.
Since the introduction of the first generation in 2013, HBM has developed the second generation (HBM2), third generation (HBM2E), fourth generation (HBM3), and fifth generation (HBM3E).
This year, HBM3e will be the mainstream in the market, with concentrated shipments expected in 2H24. Besides, the sixth generation HBM4 is anticipated to make its debut as early as 2025. Reportedly, HBM4 will bring revolutionary changes, adopting a 2048-bit memory interface, which theoretically can double the transmission speed again.
Due to high technical barriers, HBM market share is firmly at the helm of the three major memory players: SK Hynix, Samsung, and Micron. With the ongoing influence of AI, their competition has been expanding from HBM to GDDR field.
Since the beginning of this year, the three manufacturers have successively announced the availability of GDDR7 memory samples. It’s expected that some of them will start mass production of GDDR7 between 4Q24 and 1Q25.
In March, Samsung and SK Hynix announced their respective GDDR7 specifications. Samsung’s GDDR7 chip, using PAM3 signal for the first time, can achieve a speed of 32Gbps at a DRAM voltage of only 1.1V, exceeding the JEDEC GDDR7 specification of 1.2V.
SK Hynix’s latest GDDR7 product, compared to its predecessor GDDR6, offers a maximum bandwidth of 160GB/s, double that of the previous generation, with a 40% improvement in power efficiency and a 1.5 times increase in memory density.
In June, Micron announced it already begun sampling its new generation of GDDR7, achieving a speed of 32Gbps and a memory bandwidth of 1.5TB/sec, a 60% improvement over GDDR6, boasting the industry’s highest bit density. Micron’s GDDR7 utilizes 1β DRAM technology and an innovative architecture and has four independent channels to optimize workloads, offering faster response time, smoother gaming experience, and shorter processing time.
Additionally, Micron’s GDDR7 improves energy efficiency by 50% relative to GDDR6, which hence enhances thermal performance for portable devices (Like laptop) and extends battery lifespan. The new sleep mode can reduce standby power consumption by 70%. Micron claims its next-generation GDDR7 can deliver high performance, increasing throughput by 33% and reducing response time for generative AI workloads (Text and image creation included) by 20%.
Recently, rumor has it that NVIDIA RTX 50 series will fully adopt the latest GDDR7, with a maximum capacity of 16GB, including models GN22-X11 (16 GB GDDR7), GN22-X9 (16 GB GDDR7), GN22-X7 (12 GB GDDR7), GN22-X6 (8 GB GDDR7), GN22-X4 (8 GB GDDR7), and GN22-X2 (8 GB GDDR7). The industry believes that GDDR7 will become a new arena in the memory market following HBM, in which manufacturers will continue to battle for NVIDIA GPU orders.
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(Photo credit: Samsung Electronics)
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According to reports from the Chosun Daily, starting from July, the South Korean government will begin offering incentives and subsidies to semiconductor companies, launching a 26 trillion won (USD 19 billion) funding program to support the industry.
While China and the United States are introducing government funds into strategic sectors, the South Korean government is also joining this effort amid geopolitical tensions that are fragmenting the global chip supply chain.
Initially, South Korea will start with an 18 trillion won (USD 12.94 billion) investment program, including preferential loans and investment funds. According to a statement from the Ministry of Economy and Finance, eligible companies will be able to borrow from a 17 trillion won low-interest loan program.
According to the Chosun Daily, the financial support program will commence next month, providing preferential interest rates of 0.8 to 1.0 percentage points for large companies and 1.2 to 1.5 percentage points for small and medium-sized enterprises, compared to standard industrial bank loans.
Additionally, the government aims to raise up to 800 billion won for a new semiconductor ecosystem fund by 2027. By 2025, the fund plans to gather 300 billion won and will begin making equity investments in materials, components, equipment, and fabless companies starting next month.
The government is also planning to extend the tax credit scheme for developing national strategic technologies by an additional three years, which was initially scheduled to expire at the end of this year.
Before the aforementioned “comprehensive support package” announced on 26th, the South Korean government is already investing USD 470 billion to establish a massive semiconductor cluster in the suburbs of Seoul, which covers areas from Pyeongtaek to Yongin, aiming to produce 7.7 million wafers monthly by 2030.
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