According to a report from Reuters, it’s rumored that ByteDance, the parent company of TikTok, is collaborating with American chip designer Broadcom to develop an advanced AI processor, which could provide ByteDance with a steady supply of high-end chips.

On June 24th, Reuters’ report cited sources, stating that the 5nm Application-Specific Integrated Circuit (ASIC) being developed by the two companies will comply with U.S. export control regulations and will be manufactured by TSMC.

Since the introduction of advanced chip export controls by Washington in 2022, no public announcements have been made regarding the development of 5nm or more advanced chips in collaboration between Chinese and American companies.

The sources cited by the same report indicate that ByteDance’s collaboration with existing partner Broadcom can help reduce procurement costs and ensure a stable supply of high-end chips. However, TSMC will not start manufacturing this new chip this year. According to Reuters citing other sources, although the two companies have already begun the design process, they have yet reached the tape-out stage, which signifies the completion of the design phase and readiness for manufacturing.

Securing a reliable source of AI chips is crucial for ByteDance’s algorithms. In addition to TikTok, the company operates numerous popular apps, including “Doubao,” an AI chatbot service similar to ChatGPT. The report further suggests that ByteDance stockpiled a significant number of NVIDIA chips, including A100, H100, A800, and H800, ahead of the initial round of U.S. sanctions. In 2023, ByteDance allocated USD 2 billion for purchasing NVIDIA chips.

Per another previous report from Reuters, it indicated that in response to U.S. sanctions, some Chinese AI chip manufacturers decided to downgrade their self-designed processors to avoid being cut off from TSMC’s foundry services. Reportedly, MetaX and Enflame entrusted downgraded chip design schematics to TSMC late last year to comply with U.S. regulations. These two leading Chinese AI chipmakers had previously claimed that their chips could rival NVIDIA’s GPUs in performance.

The downgraded AI chips designed by NVIDIA specifically for the Chinese market, including the most advanced model “H20,” reportedly received a lackluster initial market response. Due to abundant supply and forced price reductions, currently, the H20 is reportedly cheaper than competing chips from Huawei. The chip is reportedly to be sold at approximately 100,000 yuan per unit, while Huawei 910B sold at over 120,000 yuan per unit.

A previous report by The Information also indicated that major tech companies such as Alibaba, Baidu, ByteDance, and Tencent have been instructed to reduce their spending on foreign-made chips like NVIDIA’s.

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• [News] NVIDIA Reportedly Facing Price Cut Pressure of H20 Chip in China Amid Competition with Huawei

(Photo credit: Broadcom)

According to a report by Korean media outlet Business Korea, SK Hynix recently shared its latest breakthrough on its 3D DRAM at VLSI 2024 last week, announcing that the manufacturing yield of its 5-layer stacked 3D DRAM has reached 56.1%.

This means that out of roughly 1,000 3D DRAM units manufactured on a single test wafer, about 561 functional devices were successfully manufactured, the report further explains. The experimental 3D DRAM exhibits characteristics similar to the currently used 2D DRAM, marking the first time SK Hynix has disclosed specific numbers and characteristics of its 3D DRAM development.

However, SK Hynix also noted that while 3D DRAM holds great potential, a significant amount of development is still required before it can be commercialized. The memory giant also reportedly pointed out that unlike the stable operation of 2D DRAM, 3D DRAM exhibits unstable performance characteristics, and stacking 32 to 192 layers of memory cells is necessary for widespread use.

3D DRAM is also a key development area for other major memory manufacturers like Samsung Electronics and Micron. Samsung Electronics has successfully stacked 3D DRAM up to 16 layers and plans to mass-produce 3D DRAM around 2030. Micron currently holds 30 patents related to 3D DRAM, and if there are breakthroughs in 3D DRAM technology, it could produce better DRAM products than existing ones without the need for EUV equipment.

The DRAM market remains highly concentrated, currently dominated by key players such as Samsung Electronics, SK Hynix, and Micron Technology, collectively holding over 96% of the entire market share.

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• [News] Samsung and SK hynix to Implement Hybrid Bonding with 3D DRAM
• [News] The Quiet Beginning of the 3D DRAM Market Share Battle

(Photo credit: SK Hynix)

According to a report from Korean media outlet ZDNet Korea, the yield rate for Samsung Electronics’ latest Exynos 2500 processor has improved to slightly below 20% from single digits in the first quarter. However, the current yield rate is still said to be falling short of mass production standards. It remains uncertain whether it can be used in the flagship Galaxy S25 series smartphones in the future.

The report further indicates that this yield rate is still insufficient for mass production, which typically requires yields to be increased to over 60%. Therefore, Samsung Electronics’ System LSI department reportedly plans to work on improving the yield rate of the Exynos 2500 processor in the second half of this year.

The report states that it is still uncertain whether the Exynos 2500 processor can be used in the future Galaxy S25 series flagship smartphones. Since there is still considerable time before the official launch of the Galaxy S25 series, Samsung hopes to improve the yield rate of the Exynos 2500 processor to 60% by October this year.

On the other hand, TSMC is overwhelmed with 3nm orders, with major companies like Apple, NVIDIA, AMD, Qualcomm, Intel, and MediaTek all utilizing TSMC’s 3nm process. Per a report from TechNews, during TSMC’s technology forum on May 23, the 3nm production capacity this year has more than tripled compared to last year, but this is actually still not enough, so efforts are still being made to meet customer demand.

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• [News] Major Clients Reportedly Fully Allocate TSMC’s Production Capacity Until 2026, 3nm Process in High Demand
• [News] Samsung Reportedly to Challenge Apple/TSMC with 3nm Exynos W1000

(Photo credit: Samsung)

According to a report by the Economic Daily News, TSMC has secured another AI business opportunity. Following its exclusive contract manufacturing of AI chips for tech giants such as NVIDIA and AMD, TSMC, in collaboration with its subsidiary, the ASIC design service provider Global Unichip Corporation (GUC), has reportedly made significant progress in producing essential peripheral components for AI servers, specifically high-bandwidth memory (HBM). Together, they have secured a major order for the foundational base die chips of next-generation HBM4.

TSMC and GUC typically do not comment on order details. SK Hynix, on the other hand,  has clarified in a press release to Bloomberg that it has not signed a contract with GUC for its next-generation AI memory chips, according to the Economic Daily News.

Industry sources cited by the report point out that the strong demand for AI is not only making high-performance computing (HPC) related chips highly sought after, but also driving robust demand for HBM, creating new market opportunities. This surge in demand has attracted major memory manufacturers such as SK Hynix, Samsung, and Micron to actively invest. Under the influence of AI engines, the current production capacity for HBM3 and HBM3e is in a state of supply shortage.

As AI chip manufacturing advances to the 3nm generation next year, the existing HBM3 and HBM3e, limited by capacity and speed constraints, may prevent the new generation of AI chips from reaching their maximum computational power. Consequently, the three major memory manufacturers are unanimously increasing their capital expenditures and starting to invest in the development of next-generation HBM4 products, aiming for mass production by the end of 2025 and large-scale shipments by 2026.

While memory manufacturers are delving into the research and development of next-generation HBM4, the semiconductor standardization organization JEDEC Solid State Technology Association is also busy establishing new standards related to HBM4. It’s also rumored that JEDEC will relax the stacking height limit for HBM4 to 775 micrometers, hinting that the previously required advanced packaging technology using hybrid bonding can be postponed until the next generation of HBM specifications.

Industry sources cited by the report also suggest that the most significant change in HBM4, besides increasing the stacking height to 16 layers of DRAM, will be the addition of a logic IC at the base to enhance bandwidth transmission speed. This logic IC, known as the base die, is expected to be the major innovation in the new generation of HBM4 and possibly a reason for JEDEC’s relaxation of the stacking height limitation.

On the other hand, SK Hynix has announced its collaboration with TSMC to advance HBM4 and capture opportunities in advanced packaging. Industry sources also indicate that GUC has successfully secured the critical design order for SK Hynix’s HBM4 base die.

The design is expected to be finalized as early as next year, with production to be carried out using TSMC’s 12nm and 5nm processes, depending on whether high performance or low power consumption is prioritized.

Reportedly, it’s suggested that SK Hynix’s decision to entrust the base die chip orders to GUC and TSMC is primarily because TSMC currently dominates over 90% of the CoWoS advanced packaging market used in HPC chips.

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• [News] SK Hynix Disclosed Details Regarding HBM4e, Reportedly Integrating Computing and Caching Functionalities
• [News] SK Hynix Partners with TSMC to Strengthen HBM Technological Leadership

(Photo credit: TSMC)

On June 18th, Belgium’s microelectronics research center IMEC showcased the first CMOS CFET device featuring stacked bottom and top source/drain contacts at the 2024 IEEE VLSI Technology and Circuits Symposium (2024 VLSI). Although the results were achieved using front-side lithography techniques for both contacts, imec also demonstrated the feasibility of transferring the bottom contacts to the back side of the wafer, which potentially increases the survival rate of top devices from 11% to 79%.

IMEC explained that their logic technology roadmap envisions the introduction of Complementary Field-Effect Transistor (CFET) technology into device architectures at the A7 node. Paired with advanced wiring technologies, CFET is expected to reduce the standard cell height from 5T to 4T or even lower without sacrificing performance. Among the different approaches to integrating vertically stacked nMOS and pMOS structures, monolithic integration is considered the least disruptive compared to existing nanosheet process flows.

At VLSI Symposium 2024, IMEC demonstrated for the first time a functional monolithic CMOS CFET device with both top and bottom contacts. The device features a gate length of 18nm, a gate pitch of 60nm, and a vertical distance of 50nm between the n-type and p-type. The process flow IMEC’s proposed includes two CFET-specific modules: Middle Dielectric Isolation (MDI) and stacked bottom and top contacts.

MDI is a module pioneered by IMEC to isolate the top and bottom gates and to differentiate threshold voltage settings between n-type and p-type devices. Based on modifications to the “active” multilayer Si/SiGe stack in CFET, MDI module allows for the co-integration of internal spacers—a feature unique to nanosheets that isolates the gate from the source/drain.

“We obtained the best results in terms of process control with an MDI-first approach, i.e., before source/drain recess – the step where nanosheets and MDI are ‘cleaved’ to gain access to the channel sidewalls and start source/drain epi. An innovative source/drain recess etch with ‘in-situ capping’ enables MDI-first by protecting the gate hardmask/gate spacer during the source/drain recess.” stated Naoto Horiguchi, IMEC’s CMOS device technology director, as per a report from IMEC.

The second critical module is the formation of stacked source/drain bottom and top contacts, vertically separated by dielectric isolation. Key steps involve bottom contact metal filling and etching, followed by dielectric filling and etching—all completed within the confined space of the MDI stack.

Naoto Horiguchi noted that developing bottom contacts from the front side encountered many challenges, which potentially impacts bottom contact resistance and limits the process window for top devices. At VLSI 2024, IMEC indicated that despite additional processes like wafer bonding and thinning, this design is proved feasible, making the backside bottom contact structure an attractive option for the industry. Currently, research is underway to determine the optimal contact wiring method.

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• [News] TSMC’s Latest Advancements in CFET, 3D Stacking, and Silicon Photonics

(Photo credit: IMEC)