According to a report from Nikkei citing sources, memory giant Micron Technology is building a pilot production line for advanced high-bandwidth memory (HBM) in the United States and is considering producing HBM in Malaysia for the first time to capture more demand from the AI boom.

Reported on June 19, Micron is said to be expanding its HBM-related R&D facilities at its headquarters in Boise, Idaho, which include production and verification lines. Additionally, Micron is considering establishing HBM production capacity in Malaysia, where it already operates chip testing and assembly plants.

Nikkei’s report further noted that Micron’s largest HBM production facility is located in Taichung, Taiwan, where expansion efforts are also underway. Micron is said to have set a goal to triple its HBM market share to 24-26% by the end of 2025, which would bring it close to its traditional DRAM market share of approximately 23-25%.

Earlier this month, a report from a Japanese media outlet The Daily Industrial News also indicated that Micron planned to build a new DRAM plant in Hiroshima, with construction scheduled to begin in early 2026 and aiming for completion of plant buildings and first tool-in by the end of 2027.

Per industry sources cited by TechNews, Micron is expected to invest between JPY 600 to 800 billion in the new facility, located adjacent to the existing Fab15 facility. Initially, the new plant will focus on DRAM production, excluding backend packaging and testing, with a capacity emphasis on HBM products.

Micron, along with SK Hynix, has reportedly received certification from NVIDIA to produce HBM3e for the AI chip “H200.” Samsung Electronics has not yet received approval from NVIDIA; its less advanced HBM3 and HBM2e are currently primarily supplied to AMD, Google, and Amazon.

Read more

• [News] HBM Supply Shortage Prompts Micron’s Expansion, Expected Schedule in Japan and Taiwan Revealed
• [News] Micron Slightly Raises Capital Expenditure for 2024, HBM Expected to Further Drive Revenue Growth in 2025

(Photo credit: Micron)

While TSMC faces overwhelming demand for its 3nm technology, with orders from major clients like Apple and NVIDIA pouring in, Intel has now announced its progress on the 3nm technology. According to the latest report by Tom’s Hardware, Intel 3 has entered high-volume production at two sites, the Oregon and Ireland factories, with datacenter-related applications being the node’s primary focus.

However, the capacity seems to be mainly allocated to in-house chips for now. Citing Walid Hafez, Vice President of Foundry Technology Development at Intel, the report notes that Intel’s recently launched Xeon 6 “Sierra Forest” and “Granite Rapids” processors are being manufactured with the company’s 3nm node. Eventually, Intel will utilize this production node to produce datacenter-grade processors for its customers, the report states.

According to Tom’s Hardware, in addition to the standard Intel 3, Intel will also provide various versions for its 3nm node. The semiconductor giant plans to offer Intel 3T, which supports through silicon vias and can serve as a base die. Looking ahead, Intel aims to introduce the feature-enhanced Intel 3-E for chipsets and storage applications, as well as the performance-enhanced Intel 3-PT, designed for various workloads such as AI, HPC, and general-purpose PCs.

According to the report, the Intel 3 process offers both higher performance and increased transistor density, and it supports 1.2V for ultra-high-performance applications. In terms of performance, Intel claims that the new node will deliver an 18% improvement compared to Intel 4.

Regarding major competitors’ development on the 3nm node, TSMC is reported to receive strong demand from clients like Apple and NVIDIA, booking its capacity through 2026, and possibly leading to a price increase by over 5% in the node.

Like Intel, TSMC also offers various choices for its 3nm process. The members of TSMC’s 3nm family include N3, N3E, N3P, as well as N3X and N3A.

As the existing N3 technology continues to be upgraded, N3E, which began mass production in the fourth quarter of last year, targets applications such as AI accelerators, high-end smartphones, and data centers.

N3P is scheduled for mass production in the second half of this year and is expected to become mainstream for applications in mobile devices, consumer products, base stations, and networking through 2026. N3X and N3A are customized for high-performance computing and automotive clients.

On the other hand, Samsung’s second-generation 3nm production line in South Korea will reportedly commence operations in the latter half of this year  The first product to be manufactured on this line will reportedly be the application processor (AP) for the upcoming Galaxy Watch7, tentatively named “Exynos W1000,” which is expected to be unveiled in July.

Read more

• [News] Intel CEO Gelsinger Unveils Lunar Lake Processors, Giving Credit to TSMC
• [News] CoWoS Booming, TSMC Price Hikes Reportedly Imminent

(Photo credit: Intel)

According to a report from Reuters on June 19, to further restrict China’s semiconductor industry and prevent the use of semiconductor manufacturing equipment in military applications, Alan Estevez, the U.S. Commerce Department’s Under Secretary for Industry and Security, will visit the Netherlands and Japan.

Reportedly, Estevez will visit the Netherlands and Japan, with the primary objective of further limiting China’s ability to manufacture advanced semiconductors and preventing China from using chip manufacturing equipment to enhance its military capabilities. Additionally, the U.S. may add another 11 Chinese chip companies to the restricted list.

Sources cited by the report indicate that this move includes limiting the activities of equipment suppliers such as ASML and Japan’s Tokyo Electron in the Chinese market. Special attention will be given to Chinese chip manufacturers developing high-bandwidth memory (HBM) chips.

The report from also states that in July 2023, to align with U.S. government policies aimed at curbing China’s technological advancements, Japan, home to several chip equipment manufacturers like Nikon and Tokyo Electron, imposed restrictions on the export of 23 types of machinery to China. These machines range from those used for depositing thin films on silicon wafers to etching micro-integrated circuits. Similarly, the U.S. has imposed related restrictions on American companies such as Applied Materials and Lam Research.

Following Japan, the Dutch government also restricted ASML from exporting deep ultraviolet (DUV) lithography machines to China. The U.S. has not allowed some Chinese foundries to purchase additional advanced DUV machines. Prior to this, ASML had already ceased the export of even more advanced extreme ultraviolet (EUV) lithography machines to China.

With the Netherlands imposing new restrictions on the export of advanced chip manufacturing equipment effective from January, ASML previously announced that starting from 2024, they would not be able to ship NXT:2000i and higher DUV lithography equipment to China.

Equipment below NXT:2000i, including NXT:1970i and NXT:1980i, would also be restricted from shipment to advanced process fabs in China. ASML’s Chief Financial Officer, Roger Dassen, anticipated that this will impact 10% to 15% of sales in the Chinese market in 2024.

On the other hand, it has been reported that the U.S. government is in discussions with its allies about adding another 11 Chinese chip manufacturers to the blacklist. During a visit to the Netherlands in April this year, U.S. officials attempted to prevent ASML from continuing to provide maintenance services for equipment used in China. However, since ASML’s service contracts with Chinese customers are still valid and the Dutch government lacks the extraterritorial authority to terminate these contracts, this effort faced significant challenges.

Read more

• [News] Strengthening Controls on Semiconductor Equipment Exports to China, Japan Reportedly Tightens Export Control Measures Further
• [News] ASML Reports Partial Revocation of Export Licenses for DUV Equipment

(Photo credit: iStock)

Recently, Reuters reported that NATO (North Atlantic Treaty Organization) has confirmed the first companies to receive Innovation Fund of EUR 1 billion (USD 1.1 billion). The companies are four European tech startups namely London-based AI chip manufacturer Fractile and Germany-based robotics company ARX Robotics, as well as UK manufacturers ICOMAT and Space Forge.

It’s reported that NATO has allocated funds to Fractile and ARX Robotics. Fractile aims to enable faster operation of large language model (LLM) like the one supporting ChatGPT, while ARX Robotics designs unmanned robots capable of performing tasks, from weight lifting to surveillance. ICOMAT specializes in producing lightweight materials for the automotive industry, and Space Forge has been committed to manufacturing semiconductors in orbit by leveraging space conditions such as microgravity and vacuum.

The NATO Innovation Fund was launched in summer 2022, promising investment in technologies that can enhance its defense capabilities. The fund is supported by 24 of NATO’s 32 member countries, including Finland and Sweden, which joined NATO earlier this year.

Moreover, the fund also reportedly collaborates with venture capital firms Alpine Space Ventures, OTB Ventures, Join Capital, and Vsquared Ventures to uphold further investment in deep tech on African continent.

Samsung and SK hynix, which have been rapidly advancing in the High-Bandwidth Memory (HBM) arena, now confirm their intention to incorporate hybrid bonding in the upcoming 3D DRAM technology, according to the latest report by The Elec.

While the current technology uses micro bump to connect DRAM modules, hybrid bonding, which could stack chips vertically by using through-silicon-via (TSV), can eliminate the need for micro bumps, significantly reducing chip thickness.

According to an earlier report by The Korean Economic Daily, currently, DRAM comprises up to 62 billion cells on a substrate with densely integrated transistors on a flat plane, posing challenges such as current leakage and interference.

In contrast, 3D DRAM stacks transistors into multiple layers, which is expected to widen the gaps between them, thereby reducing leakage and interference.

Therefore, to replace the current horizontal placement, a 3D DRAM chip triples capacity per unit area by vertically stacking cells. This also differs from HBM, which vertically connects multiple DRAM chips.

During the International Memory Workshop 2024 conference held in Seoul last week, SK hynix announced its intention to implement hybrid bonding in the production of 3D DRAM. On the other hand, Samsung plans to launch 3D DRAM in 2025, according to an earlier report by The Korean Economic Daily.

Meantime, Samsung is also exploring 4F Square DRAM and plans to integrate hybrid bonding into the production process. If successful, the tech giant could reduce die surface area by 30% compared to the currently commercialized 6F2 DRAM, according to sources cited by The Elec. Samsung is said to implement the 4F2 structure in DRAM using 10nm or finer nodes.

Read more

• [News] Samsung Considers Hybrid Bonding a Must for 16-stack HBM
• [News] The Quiet Beginning of the 3D DRAM Market Share Battle

(Photo credit: SK hynix)