At the SEMICON Taiwan 2024, Samsung’s Head of Memory Business, Jung Bae Lee, stated that as the industry enters the HBM4 era, collaboration between memory makers, foundries, and customers is becoming increasingly crucial.

Reportedly, Samsung is prepared with turnkey solutions while maintaining flexibility, allowing customers to design their own basedie (foundation die) and not restricting production to Samsung’s foundries.

As per anue, Samsung will actively collaborate with others, with speculation suggesting this may involve outsourcing orders to TSMC.

Citing sources, anue reported that SK hynix has signed a memorandum of understanding with TSMC in response to changes in the HBM4 architecture. TSMC will handle the production of SK hynix’s basedie using its 12nm process.

This move helps SK hynix maintain its leadership while also ensuring a close relationship with NVIDIA.

Jung Bae Lee further noted that in the AI era, memory faces challenges of high performance and low energy consumption, such as increasing I/O counts and faster transmission speeds. One solution is to outsource the basedie to foundries using logic processes, then integrate it with memory through Through-Silicon Via (TSV) technology to create customized HBM.

Lee anticipates that this shift will occur after HBM4, signifying increasingly close collaboration between memory makers, foundries, and customers. With Samsung’s expertise in both memory and foundry services, the company is prepared with turnkey solutions, offering customers end-to-end production services.

Still, Jung Bae Lee emphasized that Samsung’s memory division has also developed an IP solution for basedie, enabling customers to design their own chips. Samsung is committed to providing flexible foundry services, with future collaborations not limited to Samsung’s foundries, and plans to actively partner with others to drive industry transformation.

Reportedly, Samsung is optimistic about the HBM market, projecting it to reach 1.6 billion Gb this year—double the combined figure from 2016 to 2023—highlighting HBM’s explosive growth.

Address the matter, TrendForce further notes that for the HBM4 generation base die, SK hynix plans to use TSMC’s 12nm and 5nm foundry services. Meanwhile, Samsung will employ its own 4nm foundry, and Micron is expected to produce in-house using a planar process. These plans are largely finalized.

For the HBM4e generation, TrendForce anticipates that both Samsung and Micron will be more inclined to outsource the production of their base dies to TSMC. This shift is primarily driven by the need to boost chip performance and support custom designs, making further process miniaturization more critical.

Moreover, the increased integration of CoWoS packaging with HBM further strengthens TSMC’s position as it is the main provider of CoWoS services.

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Jun He, Vice President of Advanced Packaging Technology and Service at TSMC, stated that 3D IC is a crucial method for integrating AI chip memory with logic chips.

According to a report from TechNews, regarding the development of 2.5D CoWoS advanced packaging, which integrates eight chiplets, TSMC will use the A16 advanced process to manufacture the chiplets, and integrated them with 12 HBM4, which is expected to be launched in 2027.

Reportedly, in his speech at the Semicon Taiwan 2024 “3D IC / CoWoS for AI Summit,”  He noted that the global semiconductor market is projected to become a trillion-dollar industry by 2030, with HPC and AI being the key drivers, accounting for 40% of the market, which also make AI chips crucial drivers for 3D IC packaging.

The reasons customers choose to manufacture AI chips with 3D IC platform for multi-chiplet design would be related to their lower costs and reduced design transition burdens.

Jun He explained that by converting a traditional SoC+HBM design to a chiplet and HBM architecture, the new logic chip would be the only component that needed to be designed from scratch, while other components such as I/O and SoC can use existing process technologies. This approach reduces mass production costs by up to 76%.

Although the new architecture might increase production costs by 2%, the total cost of ownership (TCO) is improved by 22% due to these efficiencies, He noted.

However, 3D IC still faces challenges, particularly in increasing production capacity. Jun He emphasized that the key to enhancing 3D IC capacity lies in the size of the chips and the complexity of the manufacturing process.

Regarding chip size, larger chips can accommodate more chiplets, improving performance. However, this also increases the complexity of the process, which can be three times more challenging. Additionally, there are risks associated with chip misalignment, breakage, and failure during extraction.

To address these risk challenges, Jun He identified three key factors: tool automation and standardization, process control and quality, and the support of the 3DFabric manufacturing platform.

For tool automation and standardization, TSMC’s differentiated capabilities with its tool suppliers are crucial. With 64 suppliers now involved, TSMC has gained the ability to lead in advanced packaging tools.

In terms of process control and quality, TSMC utilizes high-resolution PnP tools and AI-driven quality control to ensure comprehensive and robust quality management. Finally, the 3DFabric manufacturing platform integrates 1,500 types of materials within the supply chain to achieve optimization.

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(Photo credit: TSMC)

With advanced packaging capacity at TSMC being tight, the expansion of CoWoS has garnered significant attention. According to a report from Economic Daily News, Jun He, Vice President of Advanced Packaging Technology and Service at TSMC, noted at SEMICON Taiwan 2024 that the foundry giant is rapidly expanding its advanced packaging capacity to meet customer demands.

The company expects CoWoS capacity to grow at a compound annual growth rate of over 50% from 2022 to 2026, with high-speed expansion continuing at least until 2026.

During Jun He’s keynote at the “3D IC/CoWoS for AI Summit – HIGS Series Event” on September 4, He joked that due to severe supply shortages, he refrained from including numbers in his presentation, as customer complaints about insufficient capacity were frequent.

In response to strong customer demand, Jun He revealed that TSMC will continue to rapidly expand its advanced packaging capacity through 2026, with increased construction speeds. For CoWoS capacity, the time to build an advanced packaging plant has been reduced from three to five years to within two years, or even a year and a half.

He noted that the strong demand for advanced packaging is driven by the cost reduction benefits of chiplet design. The successful development of chiplets relies on advanced packaging, prompting TSMC to actively promote the 3DFabric Alliance to accelerate innovation and development within the 3D IC ecosystem.

Mike Hung, Senior Vice President of ASE echoed Jun He’s views, noting that the industry has learned valuable lessons from the 2.5D packaging sector since its mass production in 2013. ASE has been partnering with TSMC to boost their CoWoS capacities.

He added that further standardization of equipment or materials would be advantageous for accelerating industry innovation.

Take panel-level packaging as an example, he noted that while the technology could help  increased efficiency thanks to the transition from round to square substrates, it also presents challenges in areas like equipment and materials.

Jun He added that advancing packaging requires efforts from partners in advanced packaging materials and HBM to drive progress collectively.

On the other hand, DJ Lee, Director and COO of PCB leader ZDT Group, suggested that as the industry progresses, packaging substrates will trend towards higher layers, larger areas, flatness, and precise designs. To meet the semiconductor-level requirements, substrate manufacturers will need to enhance their smart manufacturing capabilities.

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(Photo credit: TSMC)

Disappointing financial results. A 15% layoff of its workforce. Restructuring and cost-reduction plans which may include the sale of FPGA unit Altera and freezing its USD 32 billion German fab project. Now, there seems to be more bad news on the way for Intel, as its advanced nodes, specifically 18A and 20A, reportedly run into trouble.

Broadcom Regards 18A Not Ready for High-volume Production

According to Reuters and The Verge, Broadcom’s initial tests with Intel’s 18A (1.8nm-class) process did not meet expectations, creating additional pressure on the semiconductor giant’s efforts to catch up with TSMC in the foundry sector. The reports note that Broadcom tested Intel’s 18A by producing wafers with typical design patterns. However, its engineers and executives were said to be disappointed with the results, regarding the process as “not ready for high-volume production.”

A Broadcom spokesperson informed Reuters that the company has not yet completed its evaluation of Intel’s 18A, indicating that the assessment is still in progress.

The 18A node plays a crucial role in Intel’s roadmap, as it has been working on the process for years, targeting to begin mass production next year, with major clients including Microsoft, according to the Verge.

However, another report from Tom’s Hardware also suggests that a defect density below 0.5 defects per square centimeter is typically seen as a positive outcome, which Intel may have already accomplished. Citing CEO Pat Gelsinger’s previous remarks, the report notes that Intel is now below 0.4 d0 defect density, which can be considered a healthy process.

20 A Cancelled: Not a Bad Idea for Cost-reduction?

Another latest bad news, though, is that Intel announced that it will no longer use its own 20A process for the upcoming Arrow Lake processors aimed at the consumer market. In its own words, the Arrow Lake processor family will be built primarily using external partners and packaged by Intel Foundry.

The unexpected move, according to Intel, is made in order to focus resources on Intel 18A, helping the company to optimize its engineering investments.

The strategy might not be a bad idea amid Intel’s crisis, as the bypass of the 20A process altogether can help avoiding the significant capital expenditures needed to scale the node to full production, a report by Tom’s Hardware notes. By sidestepping the typically high costs associated with ramping up a new and advanced node like 20A, the company will likely make progress toward its cost-cutting objectives. The order of Arrow Lake, though, might possibly go to TSMC, the report indicates.

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(Photo credit: Intel)

SK hynix President Justin Kim shared insights on SK hynix’s current memory products and HBM-related offerings in a speech titled “Unleashing the Possibilities of AI Memory Technology.” Per a report from TechNews, he announced at Semicon Taiwan that the company would begin mass production of 12-stack HBM3e by the end of this month, marking a pivotal moment in the HBM battlefield.

He also stated that AI development is only at its first stage, with future growth expected to reach a fifth stage, where AI will interact with humans through intellect and emotion. Kim outlined AI’s key challenges, including power, heat dissipation, and memory bandwidth requirements.

The biggest challenge currently, according to Kim, is power shortages, with data centers expected to need twice the power they do now. Relying solely on renewable energy will not meet this demand, and increased power use will also generate more heat, requiring more efficient heat dissipation solutions.

Thus, SK hynix is working on AI memory that is more energy-efficient, lower in power consumption, and has greater capacity, while also offering solutions tailored to different applications.

Kim then shared the latest progress on HBM3e, noting that SK Hynix was the first supplier to produce 8-layer HBM3e and will begin mass production of 12-layer HBM3e by the end of the month. Additionally, SK Hynix introduced its latest products in DIMM, enterprise SSDs (QLC eSSD), LPDDR5T, LPDDR6, and GDDR7 as well.

Regarding technology development, Kim highlighted that HBM4 will be the first product based on a base die, combining SK hynix’s advanced HBM technology with TSMC’s cutting-edge manufacturing to achieve unparalleled performance. Mass production schedules will be aligned with customer demands.

On a global scale, Kim announced the establishment of a new facility in Yongin, South Korea, with plans to begin mass production in 2027, positioning Yongin as one of the largest and most advanced semiconductor hubs.

Moreover, SK hynix will invest in Indiana, USA, expected to start operations at a new plant in 2028, focusing on advanced HBM packaging.

Eventually, Kim stated that SK hynix will concentrate on AI business, looking to build AI infrastructure with SK Group. This includes integrating power, software, glass substrates, and immersion cooling technology, and working to become a core player in the ecosystem, overcoming challenges with partners to achieve goals in the AI era.

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