According to a report by Nikkei News, Japan’s official support for the semiconductor industry expenditure, relative to its gross domestic product (GDP), is significantly higher than that of the United States and other major Western countries.

Figures submitted by a subcommittee under Japan’s Ministry of Finance’s Fiscal System Council show that Japan will invest JPY 3.9 trillion (approximately USD 25.7 billion) over the next three years, equivalent to 0.71% of its GDP. In comparison, the United States will invest more, with JPY 7.1 trillion over five years, but this represents only 0.21% of its GDP, less than one-third of Japan’s ratio.

Over the next five years, France’s expenditure amounts to JPY 700 billion, equivalent to 0.2% of its GDP. Germany’s expenditure stands at JPY 2.5 trillion, equivalent to 0.41% of its GDP.

On Monday, the U.S. Department of Commerce announced a direct subsidy of up to USD 6.6 billion to TSMC, aiming to attract more investments from TSMC within the United States. Meanwhile, in Japan, TSMC secured approximately JPY 1.2 trillion (USD 7.5 billion).

Nikkei notes that Japan’s JPY 3.9 trillion investment in the semiconductor industry involves supplementary budgets, leading to a sharp increase in spending. Thus, the Ministry of Finance is concerned about the lack of funding sources for official support of semiconductor manufacturing. According to Nikkei News, only over JPY 500 billion of Japan’s semiconductor industry expenditures have been covered by actual funds.

One funding source is GX bonds, which the government has started issuing for economic green transformation to achieve net-zero emissions by 2050. GX bonds are expected to raise approximately JPY 20 trillion over the next decade, to be repaid using carbon tax revenue.

TrendForce has previously reported that Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

Read more

• [News] TSMC Receives USD 6.6 Billion for Chipmaking from the US Government, Commits to Constructing Third Fab
• [News] Subsidies to TSMC from Japan and China Increase Over Fivefold Annually

(Photo credit: TSMC)

At the time when Japan is strengthening the construction of its semiconductor supply chain, as per a report from the Japan Times, Japanese photoresist giant Shin-Etsu Chemical is rumored to build a chip material plant in Gunma Prefecture, Japan, which marks its first new domestic manufacturing base in Japan over the past 56 years.

It’s reported that Shin-Etsu Chemical plans to invest approximately JPY 83 billion (USD 547 million) in Isesaki City, northern Tokyo, Gunma Prefecture, Japan to construct a factory covering an area of around 150,000 square meters, which is scheduled to be completed in 2026.

This new base, to produce photoresist and other materials used in semiconductor lithography processes, will become the strategic center for Shin-Etsu Semiconductor Materials, exporting to South Korea, the United States, and other regions. The company also plans to conduct research and development there eventually.

Public data shows that Shin-Etsu Chemical holds about 20% of the global photoresist market, especially in advanced product field, where it aims to capture at least 40% market share. Currently, the company mainly produces photoresist in Taiwan and Niigata Prefecture, Japan.

Japan has long held a strong global market position in upstream semiconductor aterial markets, especially in areas such as silicon wafers and photoresist, where its market dominance remains unshaken.

Currently, many Japanese companies are expanding production and conducting research and development. Industry sources indicate that Mitsui Chemicals is expanding a factory in Yamaguchi Prefecture to produce films, which are used to protect photomasks from dust and damage during the lithography process.

Mitsui Chemicals will invest between JPY 5-9 billion and begin mass production in 2025 or 2026. Fuji Film has also started domestic production of CMP slurry for wafer polishing in Japan, and Nippon Sanso Holdings plans to start producing neon gas (Used in the chip manufacturing process) in Japan around 2026.

Read more

• [Insights] Analysis of the Global Photoresist Market in 2023

(Photo credit: TSMC)

Amid NVIDIA’s leadership in the AI wave, demand for CoWoS (Chip-on-Wafer-on-Substrate) has tripled, driving TSMC to aggressively expand CoWoS capacity, with a corresponding surge in demand for System-in-Integrated-Circuit (SoIC) solutions.

According to a report from MoneyDJ citing industry sources, it has suggested that in addition to AMD, which has already implemented SoIC in production, Apple is conducting limited trial production. Furthermore, collaborations are underway with NVIDIA and Broadcom, indicating that SoIC is poised to become TSMC’s next advanced packaging solution following CoWoS.

TSMC’s SoIC is the industry’s first high-density 3D chip stacking technology, enabling heterogeneous integration of chips with different sizes, functionalities, and nodes using Chip on Wafer packaging. Currently, production takes place at the AP6 assembly and testing facility in Zhunan, Taiwan. It’s rumored that the planned advanced packaging facility in Chiayi, Taiwan will include not only two CoWoS plants but also an SoIC facility.

AMD is the first customer to adopt SoIC technology, with its latest MI300 chip using SoIC combined with CoWoS solution. Apple, TSMC’s primary customer, is reportedly interested in SoIC and plans to incorporate it with Hybrid molding technology for Mac products. Small-scale trials are currently underway, with mass production anticipated between 2025 and 2026. NVIDIA and Broadcom are also collaborating in this field.

As per the same report citing industry sources, the SoIC technology is still in its early stages, with monthly production capacity expected to reach around 2,000 wafers by the end of this year. There are prospects for this capacity to double this year and potentially exceed 10,000 wafers by 2027.

With support from major players like AMD, Apple, and NVIDIA, TSMC’s expansion in SoIC is viewed as confident, securing future orders for high-end chip manufacturing and advanced packaging.

Read more

• [News] TSMC Reportedly Sensing Increased Orders Again, CoWoS Production Capacity Surges
• [News] TSMC’s SoIC Demand Heats Up, Reports Suggest Significant Capacity Expansion

(Photo credit: TSMC)

The global laptop and PC market is experiencing a gradual recovery, driven by the growing trend of AI-powered PCs (AIPC). Consequently, as per a report from TechNews, the competition to enhance AI chip computing power has emerged as a key global focus. 

One of the competitors, Intel, during its Vision 2024 event, showcased its next-generation laptop chip, Lunar Lake. Intel CEO Pat Gelsinger stated that this chip will deliver over 100 TOPS (trillion operations per second) of AI performance, with the NPU alone contributing 45 TOPS. This marks a threefold increase in AI performance compared to Intel’s current generation of chips and meets the 45 TOPS NPU performance threshold previously set by Intel for the next generation of AI PCs.

Currently, Intel’s Meteor Lake processor NPU can only deliver 10 TOPS, which falls short of the standard required for the next generation of AI PCs. However, the NPU performance of Lunar Lake precisely meets the 45 TOPS standard.

Pat Gelsinger did not provide detailed breakdowns of the remaining 55+ TOPS performance between the CPU and GPU, but it can be reasonably speculated that the GPU contributes around 50 TOPS, while the CPU cores contribute 5-10 TOPS.

As for Intel’s competitors, AMD’s current-generation Ryzen Hawk Point platform offers NPU performance of 16 TOPS, which is also below Intel’s envisioned standard for the next generation of AI PCs.

However, AMD has recently indicated that their next-generation products will make significant breakthroughs to meet the demands of AI computing, incorporating a robust architecture with powerful CPU, GPU, and NPU components. This design philosophy has been consistent for AMD from the Ryzen 7040 series to the current 8040 series.

At an AI event in December last year, AMD unveiled the next-generation Ryzen Strix Point mobile processor featuring the XDNA 2 architecture, boasting a threefold increase in AI performance compared to the previous generation.

Yet, AMD has not provided detailed performance allocations for each component. Nonetheless, a simple calculation suggests that if the NPU performance triples, then the NPU performance of Ryzen Strix Point would reach 48 TOPS.

Qualcomm’s Snapdragon X Elite platform represents another competitor in the escalating competition, with chips based on ARM-based architecture scheduled to launch in mid-2024. Qualcomm has stated that its NPU performance will reach 45 TOPS, further heightening the competition among Intel, AMD, and Qualcomm for dominance in the next generation of AI computing.

Read more

• [News] AMD Hosts Innovation Summit, CEO Lisa Su Highlights the Beginning of AIPC Era
• [News] PC Market on the Rise, Tremendous Potential for AIPC Next Year

(Photo credit: Intel)

As the U.S. Department of Commerce finalizes subsidies for Intel and TSMC, the two major semiconductor manufacturers will enter a new competitive landscape in the United States.

In preparation for these new challenges and with the first fab trial production imminent, sources cited by a report from Liberty Times has revealed that TSMC will dispatch Vice President of Manufacturing Operations, Arthur Chuang, to oversee the Arizona site in May. He will collaborate with TSMC’s vice president of fab operations Dr. Y.L. Wang, signaling TSMC’s accelerated efforts to establish and produce at U.S. fabs concurrently, aiming to achieve a competitive advantage in advanced manufacturing processes in the United States.

Arizona Fab to Begin Trial Production of 4,000 Wafers by Month’s End

Following the confirmation of subsidies for Intel and TSMC by the U.S. Department of Commerce, subsidies for Samsung are also rumored to be announced soon. Industry sources cited in the report from Liberty Times believe that the United States, through these subsidies promoting domestic chip manufacturing and with major clients gathering, will become the primary battlefield for investment in advanced manufacturing processes.

However, with high production costs and the need to rebuild supply chains, TSMC has adjusted its strategy following a series of setbacks at its first fab. After more than a year of installation work, the fab is nearing completion and preparing to embark on a new phase with trial production of approximately 4,000 wafers using 4-nanometer processes by the end of this month. The target is to ramp up production by the first half of 2025, making this facility the most advanced semiconductor fab in the United States.

TSMC’s U.S. fab is facing new challenges as it continues to build and produce concurrently. According to the same report citing industry sources, unlike the previous director-level executive overseeing operations at the U.S. fab, TSMC will be assigning a vice president-level executive to lead the site, with experienced fab construction veteran Arthur Chuang slated for a long-term assignment in the United States starting in May.

Arthur Chuang holds a Ph.D. in Civil Engineering from National Taiwan University and joined TSMC 35 years ago as an equipment engineer. He transitioned to fab operations over 25 years ago and has overseen the construction of nearly 20 fabs, including Fab 15 in Tainan, Fab 18 in Southern Taiwan, and the advanced 2-nanometer fab sites in Hsinchu and Kaohsiung.

TSMC’s second semiconductor fab in the United States is currently under construction, with plans announced on April 8th to commence production of next-generation 2-nanometer process technology in 2028. Additionally, a third fab is scheduled to begin mass production of 2-nanometer or more advanced process technologies by the end of 2030.

The total area of TSMC’s U.S. fab is 1,100 acres, which is more than half of its area in the Hsinchu Science Park. Estimates from the supply chain suggest that this site could accommodate up to six fabs, indicating that TSMC’s expansion plans may go beyond just building a third fab. If collaboration with U.S. partners proceeds smoothly, further expansion is also possible in the future.

TSMC’s Kumamoto Fab Phase 2 to Commence Construction by Year-End, Production Set for 2027

Additionally, TSMC’s Japan Kumamoto Fab (JASM) announced yesterday that its Phase 2 facility will be located adjacent to Phase 1 on the east side, covering an area of approximately 320,000 square meters, which is about 1.5 times the size of Phase 1. Construction is scheduled to commence by the end of this year, with production expected to start by the end of 2027.

TSMC is scheduled to hold an earnings call on April 18th, and ahead of the conference, positive news has emerged regarding the new US fab. It is anticipated that the related topics will also be the focus of attention on the day of the conference.

Read more

• [News] TSMC Receives USD 6.6 Billion for Chipmaking from the US Government, Commits to Constructing Third Fab
• [News] TSMC’s US Fab Reportedly Eyeing for Early Mass Production

(Photo credit: TSMC)