According to TrendForce’s latest memory spot price trend report, China’s 618 shopping festival has limited effects on demand, slowing down the digestion of existing inventory, causing DRAM and NAND Flash spot prices to slide further. However, DDR5 has been performing relatively better than older products such as DDR3 and DDR4 in sales. Details are as follows:

DRAM Spot Price:

Spot prices continue to decline. China’s 618 shopping festival is generating a more significant extent of purchase sentiment regarding smartphones due to huge price slashes, while other end products, having yet to exhibit any signs of recovery in demand, have slowed down the digestion of existing inventory. Generally speaking, DDR5 has been performing slightly better in sales, while older products, such as DDR3/4, are sustaining a larger decrement due to transitions of platforms. Mainstream packaged DDR4 1Gx8 2666MT/s saw a price drop of 0.84% (from US$1.904 to US$1.888) this week.

NAND Flash Spot Price:

Spot prices for NAND Flash are maintaining a slow depletion. The recent 618 e-commerce promotions have proven to be confined in efficacy towards overall market demand, where the enervation seen from transactions of consumer products continues to aggravate the inversion between contract and spot prices. 512Gb TLC wafer spots have dropped by 1.74% this week, arriving at US$3.328.

With high demand for AI chips from major players like NVIDIA and AMD, the capacity for advanced packaging falls short of meeting demand. Industry sources cited in a report from the Economic Daily News indicate that TSMC’s new CoWoS facility in the Southern Taiwan Science Park in Chiayi is now undergoing environmental impact assessments, prompting the commencement of equipment procurement.

Additionally, considering the insufficiency of planned CoWoS facilities in the Chiayi park, TSMC is reportedly sending representatives to survey additional land for potential expansion.

Regarding these developments, TSMC stated on June 11 that they do not comment on market rumors.

With the rapid development of AI applications, the demand for advanced packaging in the chip market has surged. TSMC, serving as the major foundry partner for tech giants like NVIDIA and AMD in AI chip production, has faced continuous high demand for advanced packaging capacity for some time. The company has been actively expanding related capacity and is now venturing into building a new CoWoS facility in the Southern Taiwan Science Park in Chiayi.

According to the information previously announced by the Chiayi County government, TSMC’s advanced packaging facility will occupy approximately 20 hectares in the Southern Taiwan Science Park, with the first facility covering around 12 hectares. The first advanced packaging fab is expected to be completed by the end of 2026, creating 3,000 job opportunities. TSMC initially plans to build two advanced packaging facilities in the area.

According to official information from TSMC, its backend test and packaging facilities include the Hsinchu Advanced Backend Fab 1, Southern Taiwan Science Park Advanced Backend Fab 2, Longtan Advanced Backend Fab 3, Central Taiwan Science Park Backend Advanced Fab 5, and Miaoli Zhunan Advanced Backend Fab 6.

Industry sources cited by the same report from the Economic Daily News further indicate that advanced packaging-related equipment is currently being gradually supplied to TSMC’s Zhunan, Central Taiwan, and Southern Taiwan fabs, with shipments to the Chiayi facility expected to commence from the third quarter of next year.

TSMC Chairman C.C. Wei previously mentioned that despite their efforts to increase capacity, the strong demand from customers has led to an insufficient supply, which has led to outsourcing to specialized packaging and testing foundries. He emphasized TSMC’s ongoing expansion of CoWoS advanced packaging capacity, with the goal of doubling their in-house capacity growth this year and continuing efforts into next year to narrow the gap between supply and demand.

TSMC has integrated its advanced packaging-related technologies into the “3DFabric” platform, allowing customers to select and configure according to their needs. The front-end technologies include System on Integrated Chip (SoIC), while the back-end assembly and testing technologies include Integrated Fan-Out (InFO) and the CoWoS series family.

In June 2023, TSMC announced the official opening of its Advanced Backend Fab 6 located in the Zhunan Science Park, becoming its first fully automated advanced packaging and testing facility to realize integrated front-end to back-end processes and testing services under the 3DFabric platform.

Source: TSMC

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(Photo credit: TSMC)

Starting from October, 2022, the U.S. has launched a series of export controls, targeting to limit China’s access to advanced semiconductor technologies, while tech giants including Intel, Qualcomm and NVIDIA are not allowed to ship some of their most cutting-edge chips to China. Now a new development seems to emerge, as the White House is said to consider additional restrictions on China’s access to gate-all-around (GAA) transistor technology as well as high-bandwidth memory (HBM), according to reports from Bloomberg and Tom’s hardware.

For now, the Big Three in the semiconductor industry have all announced their roadmaps regarding GAA. TSMC plans to adopt GAAFET (gate-all-around field-effect transistor) in its A16 process (2 nm), targeting for mass production in 2026. Intel aims to implement GAA in its upcoming 20A node, which may enter mass production by 2024. Samsung, on the other hand, is the only company to adopt GAA as early as in its 3nm node.

GAA transistors are crucial for pushing Moore’s Law further. By replacing the vertical fin used in FinFET transistors with a stack of horizontal sheets, the structure could further reduce leakage while increase drive current, which enables better chip performance.

Citing sources familiar with the matter, Bloomberg noted that in March, UK has imposed controls on GAAFET structures, which are typically used for chips manufactured with advanced nodes, and now the U.S. and other allies are expected to follow. The related restrictions are reportedly expected to be implemented as soon as this summer, according to the report, though further details have yet to be confirmed.

Also, it remains unclear whether the ban would restrict China’s ability to develop its own GAA chips or prevent U.S. and other international chipmakers from selling their products to Chinese firms, the report noted.

In addition to GAA, the Bloomberg report also mentioned that there have been preliminary discussions about restricting exports of high-bandwidth memory (HBM) chips. HBM chips, produced by memory giants like SK Hynix, Samsung and Micron, could enhance the performance of AI applications and are utilized by companies such as NVIDIA.

Recently, Huawei successfully mass-produced 7nm chips without using lithography technology. This development has surprised the global semiconductor market and has led to speculation that Huawei may soon also mass-produce 5nm chips. However, Zhang Ping’an, the Chief Executive Officer of Huawei Cloud Services, expressed concern earlier that China, due to US sanctions, is unable to purchase 3.5nm chip equipment.

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(Photo credit: Intel)

As the standard DRAM market experiences an unprecedented cycle of supply-demand imbalance, the shortage of DDR3 production capacity has become even more severe.

According to a report from the Economic Daily News, with leading manufacturers like Samsung exiting DDR3 production, while demand for DDR3 from AI and edge computing devices continuing to increase, the storage capacity per single device is rising sharply. This is expected to drive a rebound in DDR3 prices, potentially benefiting related Taiwanese manufacturers such as Winbond, Elite Semiconductor Microelectronics Technology (ESMT), and Etron.

In response to the shift of operational focus to high-bandwidth memory (HBM) and DDR5, the world’s top three memory manufacturers are gradually phasing out the DDR3 market.

Reportedly, Samsung has informed customers that it will cease DDR3 production by the end of the second quarter. SK Hynix had already converted its DDR3 production at its Wuxi plant in China to DDR4 by the end of last year. Meanwhile, Micron has significantly reduced its DDR3 supply to expand its DDR5 and HBM production capacity.

As per industry sources cited in the same report, it’s said that as the reduction in production by major DRAM manufacturers continues to take effect, it has driven standard DRAM prices up from the second half of 2023 to the present, with further increases expected.

Thus, prices for niche memory like DDR3 tend to lag behind standard DRAM by one to two quarters. For Taiwanese manufacturers such as Winbond, ESMT, and Etron, which focus on DDR3, the benefits of DDR3 price increases will gradually become apparent this quarter and next.

The industry sources cited by the same report also point out that DDR3 applications remain quite widespread. For example, WiFi 6 devices predominantly uses DDR3, and the next generation, WiFi 7 devices, will still primarily use DDR3/DDR4. Additionally, edge computing devices would continue to adopt DDR3. With supply significantly decreasing while demand remaining strong, DDR3 prices are expected to continue their upward trend.

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(Photo credit: Samsung)

According to the latest report by TheElec, though Samsung has been using thermal compression (TC) bonding until its 12-stack HBM, the company now confirms its belief that hybrid bonding is necessary for manufacturing 16-stack HBM.

Regarding its future HBM roadmap, Samsung reportedly plans to produce its HBM4 sample in 2025, which will mostly be 16 stacks, with mass production slated for 2026, the report noted. According to TheElec, earlier in April, Samsung used hybrid bonding equipment from its subsidiary, Semes, to produce a 16-stack HBM sample, of which it indicated to operate normally.

Citing information Samsung revealed during the 2024 IEEE 74th Electronic Components and Technology Conference last month, TheElec learned that Samsung considered hybrid bonding essential for HBM with 16 stacks and above.

According to the report, Samsung has been using thermal compression (TC) bonding until its 12-stack HBM. However, now it emphasized on hybrid bonding’s ability to reduce height, which would be indispensable for 16-stack HBM. By further narrowing the gap between chips, 17 chips (one base die and 16 core dies) can be fitted within a 775-micrometer form factor.

According to an earlier report from TechNews, Samsung and Micron use TC-NCF technology (thermal compression with non-conductive film) on HBM production, which requires high temperatures and high pressure to solidify materials before melting them, followed by cleaning. The industry has relied on traditional copper micro bumps as the interconnect scheme for packages, while their sizes pose challenges when trying to allow more chips to be stacked at a lower height.

Samsung stated that though making the core die as thin as possible or reducing the bump pitch could help, these methods have reached their limits. Sources cited by the Elec mentioned that it is very challenging to make the core die thinner than 30 micrometers. Also, using bumps to connect the chips has limitations due to the volume of the bumps. Thus, hybrid bonding technology may emerge as a promising solution.

While the current technology uses micro bump materials to connect DRAM modules, hybrid bonding, which could stack chips veritically by using through-silicon-via (TSV), can eliminate the need for micro bumps, significantly reducing chip thickness.

On the other hand, according to another report by Business Korea, SK hynix has shown its confidence in the HBM produced with Mass Reflow-Molded Underfill (MR-MUF) technology. MR-MUF technology attaches semiconductor chips to circuits, using EMC (liquid epoxy molding compound) to fill gaps between chips or between chips and bumps during stacking.

SK hynix reportedly plans to begin mass production of 16-layer HBM4 memory in 2026, and the memory heavyweight is currently researching hybrid bonding and MR-MUF for HBM4, but yield rates are not yet high, the report said.

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(Photo credit: Samsung)