SoftBank Group’s global IP leader, Arm, has reportedly announced the establishment of an AI chip division with the goal of developing AI chip prototypes by spring 2025. According to a report from DRAMeXchange, mass production will be handled by contract manufacturers, with initial production slated to begin in autumn 2025.

Arm will cover the initial development costs estimated to reach several trillion yen, funded by SoftBank Group. Once a large-scale production system is built, Arm’s AI chip business may be spun off and incorporated into a SoftBank Group division, which is because SoftBank holds a total of 90% of Arm’s shares and has been in talks with TSMC to secure production capacity.

Arm is a significant player in the global semiconductor industry, renowned for its energy-efficient Arm architecture, which commands over 90% of the global market share in smartphone chip field. SoftBank acquired Arm in 2016 for USD 32 billion, empowering Arm to go public on the US stock exchange in September 2023.

Last week, Arm reported fiscal 2024 fourth quarter revenue of USD 928 million (+47% YoY) and adjusted operating profit of USD 391 million. It forecasts first-quarter revenue for fiscal year 2025 to be USD 875-925 million, expecting annual revenue to be USD 3.8-4.1 billion.

According to Canada’s Precedence Research, the current market size for AI chips is USD 30 billion, expected to exceed USD 100 billion by 2029 and USD 200 billion by 2032. Despite NVIDIA’s dominant position in AI chip technology, it is unable to meet the growing demand.

Eyeing on the opportunities presented by the AI wave, SoftBank Group founder Masayoshi Son has identified AI as a key focus area for development and is seeking to raise USD 100 billion to found an AI chip company to compete with NVIDIA.

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• [News] SoftBank Founder Masayoshi Son Plans to Raise USD 100 Billion to Establish AI Chip Company

(Photo credit: SoftBank News)

According to a report from Korean media The Korea Economic Daily, Samsung Electronics Co. is planning to apply its 3nm process chips to its Galaxy series smartphones and smartwatches, posing a challenge to rivals Apple and TSMC.

The report cited industry sources on May 13th, stating that Samsung’s second-generation 3nm production line in South Korea is set to commence operations in the latter half of this year (2024). The first product to be manufactured on this line will reportedly be the application processor (AP) for the upcoming Galaxy Watch7, tentatively named “Exynos W1000,” which is expected to be unveiled in July.

As per the same report citing sources, the Exynos W1000 is set to utilize the semiconductor industry’s most advanced second-generation 3nm process, with computing performance and power efficiency expected to increase by over 20%. In comparison, the Apple Watch Series 9 utilizes a 5nm application processor.

On another note, industry sources cited by the same report revealed that Samsung’s next-generation flagship smartphone, the Galaxy S25, scheduled for an early 2025 release, will also feature the 3nm Exynos W1000 application processor. Samsung aims to unveil this technology ahead of the Paris Summer Olympics opening on July 26th, with a “Galaxy Unpacked” event scheduled for July 10th in Paris.

The mobile processor industry has entered the 3nm battleground. Per Wccftech’s previous report, it is rumored that TSMC’s N3E process is also used for producing products like the A18 Pro chip scheduled to be used in iPhone 16 Pro, the upcoming Qualcomm Snapdragon 8 Gen 4, and the MediaTek Dimensity 9400, among other major clients’ products.

Meanwhile, as per a report from another South Korean media outlet TheElec, Siyoung Choi, the President of Samsung’s Foundry Business, predicted during the annual shareholders’ meeting on March 20th that the second-generation 3nm process is expected to begin production in the latter half of this year, while production for the 2nm process is slated for next year.

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(Photo credit: Samsung)

Taiwan Semiconductor Manufacturing Company (TSMC) has planned to build two fabs in Kumamoto Prefecture, Japan. Kumamoto’s newly appointed governor, Takashi Kimura, who took office in April, stated in an report from Bloomberg on May 11th that he would spare no effort to persuade TSMC to establish a third fab in the region. He has already proposed a visit to TSMC’s headquarters in Taiwan this summer to discuss related matters, aiming to transform Kumamoto into a semiconductor hub.

TSMC has not responded to this matter. While TSMC’s third fab in Kumamoto, as mentioned by Governor Kimura, has not materialized yet, and TSMC has not officially announced it, Bloomberg previously reported that TSMC is considering building a third fab in Japan, which would also be located in Kumamoto and produce more advanced chips.

Regarding the rumored TSMC Kumamoto Fab 3, Takashi Kimura stated, “We are prepared to give our full support.” He expressed his hope to attract numerous semiconductor-related enterprises and research institutions to Kumamoto, aiming to establish an industrial cluster similar to Taiwan’s Hsinchu Science Park. He also hopes Kumamoto will become a birthplace for various industries stemming from semiconductors, including AI, data centers, and autonomous driving technologies.

Kimura believes that during the preparations for TSMC’s first fab in Kumamoto, the region already possesses better-quality road and water infrastructure and an education system that better supports international school students, which could be advantageous.

TSMC’s Kumamoto Fab 1, a joint investment between TSMC, Sony Semiconductor Solutions Corporation, and Denso Corporation, was inaugurated in February. TSMC stated in an earlier press release that in response to customer demand, construction of the second JASM (TSMC’s majority-owned manufacturing subsidiary in Kumamoto Prefecture) fab is slated to begin by the end of 2024. The expansion of production capacity is also expected to optimize the overall cost structure and supply chain efficiency of JASM, with operations starting by the end of 2027.

In the future, the two fabs under JASM will enable a total monthly production capacity of over 100,000 12-inch wafers, providing 40-nanometer, 22/28-nanometer, 12/16-nanometer, and 6/7-nanometer processes for automotive, industrial, consumer, and high-performance computing (HPC) applications.

Capacity planning may be adjusted according to customer demand, with the Kumamoto fab directly creating a total of over 3,400 high-tech job opportunities. Through the investment, TSMC, Sony Semiconductor, Denso Corporation, and Toyota Motor Corporation hold approximately 86.5%, 6.0%, 5.5%, and 2.0% of the JASM shares, respectively.

The Kyushu Economic Research Association estimates that these fabs will contribute JPY 10.5 trillion (USD 67.4 billion) to the economy of Kumamoto Prefecture over the next decade.

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• [News] Latest Overview on TSMC’s Global Expansion Initiatives
• [News] Rumored to Build Third Plant in Kumamoto, TSMC: Currently Focusing on Assessing the Construction of a Second Plant

(Photo credit: TSMC)

At its 2022 Tech Day, Samsung revealed the target to release advanced NAND chips with over 1000 layers by 2030. According to Wccftech, the South Korean memory giant now seems to get closer to the ambitious goal, as it plans to apply new ferroelectric” materials on the manufacturing of NAND.

At the latest VLSI Technology Symposium held in Honolulu, a doctoral student from the Electrical Engineering Department at the Korea Advanced Institute of Science and Technology (KAIST) shared how “hafnia ferroelectrics” may serve as a key enabler for low voltage & QLC 3D VNAND beyond 1K layer experimental demonstration and modeling, of which the interaction between charge trapping in the metal band and the ferroelectric switching effect could maximize the ‘positive feedback’ of dual effects, enable low operating voltage, a wide range of storage window, and negligible disturbance at a bias voltage of 9 V.

Though Samsung is not directly involved in the R&D process, according to Wccftech, the researchers are said to be directly linked to the company.

The news follows Samsung’s official announcement in April, confirming that it has begun mass production for its one-terabit (Tb) triple-level cell (TLC) 9th-generation vertical NAND (V-NAND), boasted to improve the bit density by about 50% compared to the 8th-generation V-NAND, with the number of layers reaching 290, according a report by The Korea Economic Daily.

Industry sources cited by the report also revealed that Samsung’s future tenth-generation V-NAND is expected to reach 430 layers, which is scheduled to be released next year. Now the NAND ceiling may be able to hit 1000 layers, if the new ferroelectric materials work out fine.

Before Samsung, major storage giants such as Micron and SK Hynix had already surpassed the 200-layer milestone. Micron reached 232 layers with a storage density of 19.5Gb per square millimeter, while SK Hynix achieved 238 layers with a storage density of 14.4Gb per square millimeter. In early May, South Korea’s media outlet TheElec also revealed that SK Hynix has been exploring the potential of manufacturing 3D NAND at ultra-low temperatures, which may enable the company to produce its new-generation product with over 400 layers, with the help of Tokyo Electron (TEL).

(Photo credit: Samsung)

The South Korean government is said to be planning to introduce a comprehensive chip investment and research support plan, surpassing KRW 10 trillion (roughly USD 7.3 billion) in scale, to enhance its position in the critical semiconductor industry, as per a report from Economic Daily News.

According to a statement released by the South Korean Ministry of Planning and Finance on May 12th, Minister Choi Sang-mok stated during a meeting with local chip material, component, and equipment manufacturers that Seoul authorities are preparing a support scheme exceeding KRW 10 trillion in scale to aid all areas of the chip industry, including fabless semiconductor companies, chip materials, manufacturing equipment, etc., with details of this plan set to be announced shortly.

This plan may involve policy financing from the Korea Development Bank and the establishment of new funds through collaboration between state-owned and private financial institutions.

Given that large corporations like Samsung Electronics and SK Hynix already possess substantial resources, the South Korean government’s plan aims to support investments in small and medium-sized enterprises and in the backend process sector. This support will extend to investments in materials, components, equipment, chip design, and packaging processes to nurture the semiconductor ecosystem evenly.

Previously, South Korea announced the development of a large-scale chip cluster in the southern city of Yongin, with a total investment of USD 470 billion, looking to become the world’s largest semiconductor high-tech park.

As the United States and Japan continue to launch subsidy battles to attract semiconductor manufacturers to their respective countries, South Korea is also preparing a response plan.

The US government previously approved subsidies of up to USD 8.5 billion for US chip giant Intel and USD 6.6 billion for TSMC from CHIPs Act to alleviate future semiconductor supply constraints. The US government also announced on April 15th that it will provide up to USD 6.4 billion in subsidies to South Korean semiconductor giant Samsung Electronics for expanding advanced chip production capacity at its Texas plant.

In comparison, figures submitted by a subcommittee under Japan’s Ministry of Finance’s Fiscal System Council show that Japan will invest JPY 3.9 trillion (approximately USD 25.7 billion) over the next three years, equivalent to 0.71% of its GDP.

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• [News] Samsung Receives USD 6.4 Billion Subsidy from US Government, Less than Intel and TSMC
• [News] Nikkei Highlights Japan’s Chip Subsidies Exceeding GDP Ratio of US, Germany, and France

(Photo credit: Samsung)