As Moore’s Law progresses, transistors are becoming smaller and denser, with more layers stacked on top of each other. This may require passing through 10 to 20 layers of stacking to provide power and data signals to the transistors below, leading to increasingly complex networks of interconnects and power lines. Simultaneously, as electrons transmit downward, IR drop phenomena occur, resulting in power loss.

Apart from power loss, the occupation of space by power supply lines is also a concern, which often occupies at least 20% of resources. Addressing the issue of signal network and power supply network resource contention to miniaturize components becomes a major challenge for chip designers. As per a report from TechNews, this has led the semiconductor industry to begin shifting power supply networks to the backside of chips.

• TSMC’s Super Rail Technology Set to Revolutionize Chip Efficiency with A16 Process Node Debut in 2025

Leading semiconductor foundry TSMC recently unveiled its A16 process at a technical forum in North America.

This new node not only accommodates more transistors, enhancing computational efficiency, but also reduces energy consumption. Of particular interest is the integration of the Super PowerRail architecture and nanosheet transistors in the A16 chip, driving the development of data center processors that are faster and more efficient.

Notably, TSMC’s A16 employs a different chip wiring manner, with power wires delivering electricity to transistors located beneath rather than above them, known as backside power supply, facilitating the production of more efficient chips.

In fact, one of the methods to optimize processors is to alleviate IR drop, a phenomenon that reduces the voltage received by the transistors on the chip, consequently affecting performance. The A16 wiring is less prone to voltage drops, simplifying power distribution and allowing for tighter chip packaging, aiming to accommodate more transistors to enhance computational capabilities.

Additionally, TSMC’s A16 process technology directly connects the power transmission lines to the source and drain of the transistor, which improves chip efficiency.

Using the Super PowerRail in A16, TSMC achieves an 10% higher clock speed or a 15% to 20% decrease in power consumption at the same operating voltage (Vdd) compared to N2P. Moreover, the chip density is increased by up to 1.10 times, supporting data center products.

• Intel’s PowerVia Set for Production on Intel 20A in 2024

Similar to TSMC’s Super PowerRail, Intel has also introduced its backside power delivery solution, PowerVia.

According to Intel, power lines typically occupy around 20% of the space on the chip surface, but PowerVia’s backside power delivery technology saves this space, allowing  more flexibility in the interconnect layers.

In addition, the Intel team previously created the Blue Sky Creek test chip to demonstrate the benefits of backside power delivery technology. Test results indicated that most areas of the chip achieved over 90% cell utilization, with a 30% platform voltage droop improvement, 6% frequency benefit, increased unit density, and potential cost reduction. The PowerVia test chip also exhibited excellent heat dissipation properties, aligning with expectations for higher power density as logic shrinks.

Furthermore, PowerVia is slated to be integrated into Intel Foundry Services (IFS), enabling faster achievement of product efficiency and performance enhancements for customer-designed chips.

According to official documentation from Intel, the tech giant plans to implement PowerVia on Intel 20A process technology along with the RibbonFET architecture for the full-surround gate transistor. Production readiness is expected in the first half of 2024, with initial steps being taken at the fabrication plant for future mass production of client ARL platforms.

• Samsung Plans to Implement SF1.4 Process by 2027

In addition to leading the transition to GAA transistor technology, Samsung, another competitor of TSMC, is also wielding its Backside Power Delivery Network as a key weapon in the pursuit of advanced processes.

According to a previous report from Samsung, Jung Ki-tae Jung, Chief Technology Officer of Samsung’s foundry division, announced plans to apply the backside power delivery technology to the 1.4-nanometer process by 2027.

Reports from Korean media outlet theelec indicate that compared to traditional front-end power delivery networks, Samsung’s backside power delivery network successfully reduces wafer area consumption by 14.8%, providing more space on the chip to accommodate additional transistors, thereby enhancing overall performance.

Additionally, wiring length is reduced by 9.2%, aiding in resistance reduction to allow more current flow, leading to lower power consumption and improved power transmission conditions. Samsung Electronics representatives noted that the mass production timeline for semiconductor chips adopting backside power delivery technology may vary depending on customer schedules, and Samsung is currently investigating customer demand for the application of this technology.

Read more

• [News] More Complex than Intel’s? TSMC’s Super PowerRail – Elevating Chip Performance through Advanced Power Delivery
• [News] Battle of the Titans in the Angstrom Era – TSMC’s A16 Competes with Intel’s 14A and Samsung’s SF1.4

The U.S. government has reportedly revoked the licenses of Intel and Qualcomm to supply semiconductor chips used in laptops and handsets to Huawei. According to Reuters citing sources, some companies received notices on May 7th, and the revocation of the licenses took immediate effect.

In April, Huawei unveiled its first AI-supported laptop, the MateBook X Pro, equipped with an Intel Core Ultra 9 processor. This announcement drew criticism from Republican lawmakers in the United States, who argued that the Commerce Department allowed Intel to export chips to Huawei. Notably, the sources cited in a report by Reuters on March 12th once stated that Intel’s competitor, AMD, had applied for a similar license to sell comparable chips in early 2021 but did not receive approval from the US Department of Commerce.

In response to the matter surrounding Intel and Huawei, the Commerce Department confirmed the revocation of some export licenses to Huawei but declined to provide further details. Still, revoking the licenses not only damages Huawei but may also impact U.S. suppliers with business relationships with the company.

According to a report from Bloomberg, Qualcomm, which obtained a license in 2020, has been selling older 4G networking chips to Huawei, but the company expects its business to gradually decrease next year.

Another report from Reuters also indicated that Qualcomm continues to license its 5G technology portfolio to Huawei, allowing the latter to use HiSilicon’s 5G chips since last year, raising concerns of violating U.S. sanctions. Additionally, according to the same report, documents submitted by Qualcomm this month indicated that its patent agreement with Huawei will expire in the fiscal year 2025, which is earlier than expected, thus prompting negotiations for renewal agreements to begin sooner. Qualcomm has not responded to these reports.

Due to concerns over potential espionage activities by Huawei, the White House included Huawei in the trade restriction list in 2019, which requires suppliers to apply for licenses before shipping goods to blacklisted companies. However, despite this, Huawei suppliers still obtained licenses worth billions of USD to sell goods and technology to the Chinese tech giant, including allowing Intel to sell CPUs starting in 2020.

Republican Representative Elise Stefanik believes that revoking the licenses will strengthen U.S. national security, protect U.S. intellectual property rights, and thus weaken the technological advancement capabilities of communist China.

Previously, U.S. Commerce Secretary Gina Raimondo pointed out that the new chips introduced by Huawei are not as capable and lag behind U.S. chips by several years in performance, indicating that U.S. export controls on China are effective.

Read more

• [News] US Considers Sanctioning Huawei-Linked Chinese Chip Network, Huawei-Related Enterprises Blacklisted
• [News] U.S. Department of Commerce Claims Huawei Chips Not as Advanced, Lag Behind U.S. Chips by Several Years
• [News] Bypassing U.S. Restrictions? CXMT Showcases GAA Technology for 3nm Chips

(Photo credit: iStock)

According to a report from Nikkei News, US chip giant Intel will join forces with 14 Japanese companies to develop automation technology for “backend” semiconductor processes such as packaging. The aim is said to achieve automation by 2028, highlighting efforts by both the US and Japan to collaborate and reduce geopolitical risks in the semiconductor supply chain.

Intel’s collaborating partners include Japanese firms such as Omron, Yamaha Motor, Resonac, and Shin-Etsu Polymer, a subsidiary of Shin-Etsu Chemical Industry. The alliance, led by Intel Japan’s Managing Director Kunimasa Suzuki, plans to invest hundreds of billions of Japanese Yen in research and development, aiming to demonstrate technological achievements before 2028.

In the semiconductor field, as “frontend” process technologies such as circuit formation approach physical limits, the focus of technological competition is gradually shifting to “backend” processes such as chip stacking to enhance performance.

Most semiconductor backend processes are currently carried out through manual labor, leading to the concentration of factories in China and Southeast Asian countries with abundant labor force. However, to establish plants in countries like the US and Japan, where labor costs are higher, industry players consider automation technology as a crucial prerequisite.

Led by Intel, the alliance plans to establish backend production lines in Japan in the coming years, aiming for full automation. They also intend to standardize backend technologies to manage and control manufacturing, inspection, and equipment processing procedures under a single system.

According to data from the Japanese Ministry of Economy, Trade and Industry, Japanese companies currently hold a 30% share of the global semiconductor production equipment market and dominate approximately half of the semiconductor materials market.

It is widely expected that the Japanese Ministry of Economy, Trade and Industry will allocate hundreds of billions of Japanese Yen in subsidies for this project. The Japanese government has allocated approximately JPY 4 trillion (around USD 26 billion) from fiscal year 2021 to 2023 to support key industries contributing to economic security.

In April of this year, Japan approved a subsidy of JPY 53.5 billion to Rapidus to assist in backend technology development. Additionally, there are considerations to offer incentives to attract global backend capacity providers to establish operations in Japan.

Japanese and American policymakers are attempting to keep most of the chip manufacturing processes within their own territories, aiming to reduce risks in critical supply chains.

TrendForce has previously reported that Japan’s resurgence in the semiconductor arena is palpable, with the Ministry of Economy, Trade, and Industry fostering multi-faceted collaborations with the private sector. With a favorable exchange rate policy aiding factory construction and investments, the future looks bright for exports.

Read more

• [News] Overseas Expansion of Testing and Packaging Facilities – Japan, Malaysia, and Singapore Emerge as Top Choices
• [News] Rapidus Focuses on Small Clients, Diversifies into Japan to Mitigate US Geopolitical Risks

(Photo credit: Intel)

According to TrendForce’s latest memory spot price trend report, due to a significant increase in DRAM module contract prices, some buyers are turning to spot inquiries, leading to partial transactions at lower prices. Meanwhile, NAND Flash prices have shown loosening in spot prices as certain module manufacturers adopt a more cautious approach towards future wafer price trends, reducing their inventory buildup. Details are as follows:

DRAM Spot Price:

Spot prices of DRAM chips have yet to rebound, and the overall chip transaction volume has been limited due to the tepid demand situation. Regarding DRAM modules, some spot transactions have been arranged in the lower price range as a few buyers experiencing significant increases in the contract market have sought quotes in the spot market. Currently, the May Day holiday is taking place in China, so the spot market has been rather quiet in recent days. Looking ahead, an important market indicator is whether inventory-related preparations for the 618 Sales Event will lead to a notable demand increase. The average spot price of the mainstream chips (i.e., DDR4 1Gx8 2666MT/s) has not changed from last week and is holding steady at US$1.949.

NAND Flash Spot Price:

A number of module houses, who are reserved towards future wafer price trends, are no longer building significant inventory in order to achieve austerity to maintain their cash required for operations. This has led to a loosening in spot prices. Suppliers are attempting to avoid another predicament of excessive provision by controlling product availability, though such action has proven to be quite restricted pertaining to the increase of packaged die prices. Spot prices of 512Gb TLC wafers have dropped by 0.99% this week, arriving at US$3.708.

SK Hynix has been exploring the potential of manufacturing 3D NAND at ultra-low temperatures, which may enable the South Korean memory giant to produce its new-generation product with over 400 layers, South Korea’s media outlet TheElec revealed.

According to the report, instead of testing in its own wafer fabs, SK Hynix has sent test wafers to Tokyo Electron (TEL) to test the performance of the latter’s latest cryogenic etching tool. Unlike existing ones, which usually operate at 0~30°C, the Japanese fab equipment maker’s new etching equipment is capable of performing high-speed etching at -70°C.

According to a press release by TEL, its latest memory channel hole etch technology enables a 10-µm-deep etch with a high aspect ratio in just 33 minutes. It can also reduce the global warming potential by 84% compared with previous technologies.

Industry sources cited by the report indicated that SK Hynix plans to utilize a triple-stack structure for 321-layer NAND. However, when it comes to etching in deep channel holes, achieving uniformity is a major challenge. As a result, companies usually adopt double or even triple-stack structures for 3D NAND manufacturing due to the considerable difficulty in etching vertical holes.

With the help of TEL’s new etching equipment, it may be possible in the future to manufacture 3D NAND with over 400 layers, even in structures with fewer stacked layers, allowing memory manufacturers to reduce costs thanks to simplified processes. SK Hynix aims to produce 3D NAND products with over 400 layers, and depending on their performance, these NAND chips may adopt single or double-stack structures.

(Photo credit: SK hynix)