With the skyrocketing demand for AI, cloud service providers (CSPs) are hastening the development of in-house chips. Apple, making a surprising move, is actively developing a data center-grade chip codenamed “Project ACDC,” signaling its foray into the realm of AI accelerators for servers.

As per a report from global media The Wall Street Journal, Apple is developing an AI accelerator chip for data center servers under the project name “Project ACDC.” Sources familiar with the matter revealed that Apple is closely collaborating with TSMC, but the timing of the new chip’s release remains uncertain.

Industry sources cited by the same report from Commercial Times disclosed that Apple’s AI accelerator chip will be developed using TSMC’s 3-nanometer process. Servers equipped with this chip are expected to debut next year, further enhancing the performance of its data centers and future cloud-based AI tools.

Industry sources cited in Commercial Times‘ report reveal that cloud service providers (CSPs) frequently choose TSMC’s 5 and 7-nanometer processes for their in-house chip development, capitalizing on TSMC’s mature advanced processes to enhance profit margins. Additionally, the same report also highlights that major industry players including Microsoft, AWS, Google, Meta, and Apple rely on TSMC’s advanced processes and packaging, which significantly contributes to the company’s performance.

Apple has consistently been an early adopter of TSMC’s most advanced processes, relying on their stability and technological leadership. Apple’s adoption of the 3-nanometer process and CoWoS advanced packaging next year is deemed the most reasonable solution, which will also help boost TSMC’s 3-nanometer production capacity utilization.

Generative AI models are rapidly evolving, enabling businesses and developers to address complex problems and discover new opportunities. However, large-scale models with billions or even trillions of parameters pose more stringent requirements for training, tuning, and inference.

Per Commercial Times citing industry sources, it has noted that Apple’s entry into the in-house chip arena comes as no surprise, given that giants like Google and Microsoft have long been deploying in-house chips and have successively launched iterative products.

In April, Google unveiled its next-generation AI accelerator, TPU v5p, aimed at accelerating cloud-based tasks and enhancing the efficiency of online services such as search, YouTube, Gmail, Google Maps, and Google Play Store. It also aims to improve execution efficiency by integrating cloud computing with Android devices, thereby enhancing user experience.

At the end of last year, AWS introduced two in-house chips, Graviton4 and Trainium2, to strengthen energy efficiency and computational performance to meet various innovative applications of generative AI.

Microsoft also introduced the Maia chip, designed for processing OpenAI models, Bing, GitHub Copilot, ChatGPT, and other AI services.

Meta, on the other hand, completed its second-generation in-house chip, MTIA, designed for tasks related to AI recommendation systems, such as content ranking and recommendations on Facebook and Instagram.

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(Photo credit: Apple)

According to a report from Economic Daily News citing The Wallstreet Journal, Apple is rumored to be developing its own AI chips tailored for data centers, which could potentially give the world’s top smartphone seller a crucial advantage in the AI arms race. The report, quoting sources familiar with the matter, stated that Apple has been working closely with its chip manufacturing partner TSMC to design and produce these chips in the primary stage. However, it is still unclear whether the final version has been produced yet.

It is suggested that Apple’s server chips may focus on executing AI models, particularly in AI inference, rather than AI training, where Nvidia’s chips currently dominate.

Over the past decade, Apple has gradually become a major player in chip design for products like iPhone, iPad, Apple Watch, and Mac. The latest project involving Apple chips for data center servers, internally named “Project ACDC” (short for Apple Chips in Data Center), will integrate Apple’s IC design capabilities into the operation of clients’ servers, sources said.

The project has been in operation for several years, though the timetable for launching this server chip remains unclear. Apple is expected to unveil more new AI products and AI-related updates at its Worldwide Developers Conference (WWDC) in June.

An Apple spokesperson declined to comment on the reported developments.

According to reports from Wccftech on April 23rd, Apple is said to be working on a self-developed AI server processor using TSMC’s 3-nanometer process, with plans for mass production expected in the second half of 2025.

Wafer foundries’ mature process continues to suffer from oversupply, facing further price reduction pressure. According to a report from Economic Daily News, industry sources from IC design companies revealed that in this quarter, prices for certain mature processes have dropped by single-digit percentages (1% to 3%). Given the current situation, prices in the third quarter may drop by another 1% to 3%, leading to a continuous correction in overall price trends starting from the third quarter of 2022, marking the ninth consecutive quarterly decline.

Industry sources cited by the same report pointed out that this wave of price reductions in mature process was triggered by Chinese foundries two to three years ago, with Taiwanese manufacturers subsequently following suit. Major Taiwanese foundries involved in mature processes, include UMC, Vanguard International Semiconductor (VIS), and PSMC, have all been closely monitoring the latest market changes.

Regarding rumors of further price cuts in the market, UMC stated that the company would not make further comments. VIS, on the other hand, mentioned during a recent earnings call that the price pressure from Chinese foundries has affected its operations, but the company will not engage in these price-cutting competitions. It is expected that as market inventory adjustments approach completion, prices should gradually stabilize without significant fluctuations. PSMC indicated that they have not particularly felt any price pressure.

Local foundries stated that even though customers from specific applications, including driver ICs and other IC design houses, turn to Chinese foundries in order to enjoy cheaper manufacturing prices, they will not engage in price-cutting. After all, price wars may never see an end. Instead, Taiwanese foundries will continue to increase orders from other applications to gradually boost capacity utilization rates.

In the third quarter of 2022, as market conditions reversed, Chinese foundries initiated price cuts, prompting some Taiwanese manufacturers to make slight concessions in pricing. The pricing gap between Chinese and Taiwanese foundries generally remained at double-digit percentages.

To cope with a period of market inventory adjustment, some foundries are more flexible in negotiations, while others hope for customers to “exchange volume for price.”

Overall, foundry pricing has experienced eight consecutive declines up to this quarter. However, with no significant recovery in most end-demand sectors, IC design companies assess that foundry pricing in the third quarter may continue to trend downward.

Industry sources cited by the report believe that Chinese foundries receive official subsidies, allowing them to disregard profit considerations. Previously, IC design houses’ price negotiations with Chinese foundries were mostly successful, which results in single-digit percentage price reductions recently. However, after the third quarter, the room for further price reductions may diminish, indicating that the price seems to be soon hit the bottom.

However, fin order to cope with the current macroeconomic fluctuations, some IC design companies mentioned that after suffering from being “burned” by high inventory in the past, they now tend to wait for clear demand from customers before starting production. In recent years, the proportion of production sent to Chinese foundries has been increasing due to cost considerations. With the continuous expansion of mature process capacity in Chinese foundries, the pressure of oversupply may persist for a while longer.

According to TrendForce’s previous report on the fourth quarter of 2023, global semiconductor foundry revenue rankings showed that the top three semiconductor foundries globally were TSMC, Samsung, and GlobalFoundries, which are all less exposed to mature nodes.

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(Photo credit: TSMC)

Samsung Electronics and Synopsys jointly announced that the former has successfully taped out its first mobile system-on-chip (SoC) with its 3nm gate-all-around (GAA) process. According to Synopsys, Samsung used the Synopsys.ai EDA suite to help with the SoC’s layouts as well as design verification, to enhance its performance.

While it is important that Samsung utilized the Synopsys.ai suite for developing high-performance SoCs, it is also momentous progress as the semiconductor heavyweight finally tapes out its advanced smartphone APs with the node.

The unnamed high-performance mobile SoC from Samsung adopts a universal CPU and GPU architecture, along with various IP modules from Synopsys. The design team not only leveraged the Synopsys.ai EDA suite for fine-tuning designs, but the Synopsys DSO.ai to maximize its output. In addition, Samsung also targeted to achieve higher performance, lower power consumption, and optimized chip area (PPA) by leveraging Synopsys’ Fusion Compiler RTL-to-GDSII solution.

Although Samsung’s foundry has been using the GAA-based SF3E node for chip production over the past two years, it has never been used to produce chips in its own smartphones, nor on other SoCs. So far, the SF3E node has only been utilized for cryptocurrency mining chips, possibly due to the initially low yields of GAAFET nodes.

Though Samsung’s press release only indicates that this SoC has been produced with GAA nodes, and the company possesses more complex SF3 processes in addition to the first generation 3-nanometer SF3E, it is reasonable to speculate that it is SF3 given the timeline.

Kijoon Hong, vice president of SLSI at Samsung Electronics, stated that the company’s long-term collaboration with Synopsys enables leading SoC designs, showcasing the highest performance, power efficiency, and chip area on advanced mobile CPU cores and SoC designs. The tape out represents an important milestone, as it demonstrates how AI-driven solutions can help realize goals. With the help of the most advanced GAA transistor architecture, ultra-high-yield design systems can be established.

This SoC chip achieves a maximum clock speed increase of 300MHz and a 10% reduction in power consumption. Samsung’s SoC development team also utilized techniques such as design partitioning optimization, multi-source clock synthesis (MSCTS), and intelligent routing optimization to reduce signal interference, while other simpler layering methods have also been employed. According to official statements, with the boost of the Synopsys Fusion Compiler, the development process could skip weeks of ‘manual’ design time.”

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(Photo credit: Samsung)

At TSMC’s North America Technology Symposium, per a report from TechNews, the semiconductor giant unveiled its A16 process, designed to accommodate more transistors, enhance computational performance, and reduce power consumption. Of particular interest is the integration of the Super PowerRail architecture and nanosheet transistors in the A16 chip, driving faster and more efficient development of data center processors.

As Moore’s Law progresses, transistors become smaller and denser, with an increasing number of stacked layers. It may require passing through 10 to 20 layers of fstacking to provide power and data signals to the transistors below, leading to increasingly complex networks of interconnections and power lines. When electrical signals travel downward, there is IR voltage drop, resulting in power loss.

In addition to power loss, the space occupied by power supply lines is also a concern. In the later stages of chip manufacturing, complex layout of power supply lines often occupies at least 20% of resources. Solving the problem of signal network and power supply network resource conflicts, and enabling component miniaturization, has become a major challenge for chip designers. The industry, per the report, is beginning to explore the possibility of moving power supply networks to the backside of the chip.

TSMC’s A16 employs a different chip wiring. The wires that deliver power to the transistors will be located beneath the transistors instead of above them, known as backside power delivery.

Source: TSMC

One of the methods to optimize processors is to mitigate IR drop. This phenomenon lowers the voltage received by the transistors, thus lowering performance. A16’s wiring is less prone to voltage drop, and similarly, Intel also introduced backside power delivery in Intel 20A, not only simplifying power distribution but also allowing for denser chip packaging. The goal is to fit more transistors into the processor to enhance computational power.

Transistors consist of four main components: the source, drain, channel, and gate. The source is where current enters the transistor, the drain is where it exits, and the channel and gate orchestrate the movement of electrons.

TSMC’s A16 directly connects the power transmission lines to the source and drain, making it more complex than other backside power delivery methods like Intel’s. However, TSMC states that the decision for a more complex design aims to enhance chip efficiency.

Using the Super PowerRail in A16, TSMC achieves an 10% higher clock speed or a 15% to 20% decrease in power consumption at the same operating voltage (Vdd) compared to N2P. Moreover, the chip density is increased by up to 1.10 times, supporting data center products.

Source: TSMC

A16 also incorporates NanoFlex, a type of nanosheet transistor. NanoFlex provides chip designers with flexible N2 standard components, serving as the fundamental building block for chip design. Components with lower height can save space and offer higher power efficiency, while those with higher height maximize performance.

Optimizing the combination of high and low components in the same design block allows for the adjustment of power consumption, performance, and area to achieve the best balance. This capability combines various transistor types with different power efficiency, speed, and size configurations. Flexibility enables customers to tightly integrate TSMC chips with their requirements, maximizing performance.

TSMC plans to debut NanoFlex in the 2-nanometer process, with mass production scheduled for 2025. A16 is expected to launch in the second half of 2026.

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